Lines Matching defs:Pred

558   for (SDep &Pred : SU->Preds) {
559     ReleasePred(SU, &Pred);
560     if (Pred.isAssignedRegDep()) {
565       SUnit *RegDef = LiveRegDefs[Pred.getReg()]; (void)RegDef;
566       assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) &&
568       LiveRegDefs[Pred.getReg()] = Pred.getSUnit();
569       if (!LiveRegGens[Pred.getReg()]) {
571         LiveRegGens[Pred.getReg()] = SU;
841   for (SDep &Pred : SU->Preds) {
842     CapturePred(&Pred);
843     if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){
845       assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() &&
848       LiveRegDefs[Pred.getReg()] = nullptr;
849       LiveRegGens[Pred.getReg()] = nullptr;
850       releaseInterferences(Pred.getReg());
1059   for (SDep &Pred : SU->Preds) {
1060     if (Pred.isCtrl())
1061       ChainPreds.push_back(Pred);
1062     else if (isOperandOf(Pred.getSUnit(), LoadNode))
1063       LoadPreds.push_back(Pred);
1065       NodePreds.push_back(Pred);
1075   for (const SDep &Pred : ChainPreds) {
1076     RemovePred(SU, Pred);
1078       AddPredQueued(LoadSU, Pred);
1080   for (const SDep &Pred : LoadPreds) {
1081     RemovePred(SU, Pred);
1083       AddPredQueued(LoadSU, Pred);
1085   for (const SDep &Pred : NodePreds) {
1086     RemovePred(SU, Pred);
1087     AddPredQueued(NewSU, Pred);
1184   for (SDep &Pred : SU->Preds)
1185     if (!Pred.isArtificial())
1186       AddPredQueued(NewSU, Pred);
1357   for (SDep &Pred : SU->Preds) {
1358     if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU)
1359       CheckForLiveRegDef(Pred.getSUnit(), Pred.getReg(), LiveRegDefs.get(),
1971       auto &Pred = TempSU->Preds[P];
1972       if (Pred.isCtrl()) continue;  // ignore chain preds
1973       SUnit *PredSU = Pred.getSUnit();
1994     for (const SDep &Pred : TempSU->Preds) {
1995       if (Pred.isCtrl()) continue;  // ignore chain preds
1996       SUnit *PredSU = Pred.getSUnit();
2097   for (const SDep &Pred : SU->Preds) {
2098     if (Pred.isCtrl())
2100     SUnit *PredSU = Pred.getSUnit();
2146   for (const SDep &Pred : SU->Preds) {
2147     if (Pred.isCtrl())
2149     SUnit *PredSU = Pred.getSUnit();
2189   for (const SDep &Pred : SU->Preds) {
2190     if (Pred.isCtrl())
2192     SUnit *PredSU = Pred.getSUnit();
2271   for (const SDep &Pred : SU->Preds) {
2272     if (Pred.isCtrl())
2274     SUnit *PredSU = Pred.getSUnit();
2366   for (const SDep &Pred : SU->Preds) {
2367     if (Pred.isCtrl()) continue;  // ignore chain preds
2377   for (const SDep &Pred : SU->Preds) {
2378     if (Pred.isCtrl()) continue;
2379     const SUnit *PredSU = Pred.getSUnit();
2436   for (const SDep &Pred : SU->Preds) {
2437     if (Pred.isCtrl()) continue;
2438     Pred.getSUnit()->isVRegCycle = true;
2448   for (const SDep &Pred : SU->Preds) {
2449     if (Pred.isCtrl()) continue;  // ignore chain preds
2450     SUnit *PredSU = Pred.getSUnit();
2454       Pred.getSUnit()->isVRegCycle = false;
2466   for (const SDep &Pred : SU->Preds) {
2467     if (Pred.isCtrl()) continue;  // ignore chain preds
2468     if (Pred.getSUnit()->isVRegCycle &&
2469         Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
2975     for (const SDep &Pred : SU.Preds)
2976       if (Pred.isCtrl() && Pred.getSUnit()) {
2978         SDNode *PredND = Pred.getSUnit()->getNode();
2999     for (const SDep &Pred : SU.Preds)
3000       if (!Pred.isCtrl()) {
3001         PredSU = Pred.getSUnit();