Lines Matching defs:isSigned

132                         TargetLowering::ArgListTy &&Args, bool isSigned);
133   std::pair<SDValue, SDValue> ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
143   SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
2064                                             bool isSigned) {
2095   bool signExtend = TLI.shouldSignExtendTypeInLibCall(RetVT, isSigned);
2118                                             bool isSigned) {
2126     Entry.IsSExt = TLI.shouldSignExtendTypeInLibCall(ArgVT, isSigned);
2131   return ExpandLibCall(LC, Node, std::move(Args), isSigned);
2213 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2228   return ExpandLibCall(LC, Node, isSigned).first;
2252   bool isSigned = Opcode == ISD::SDIVREM;
2257   case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
2258   case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2259   case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2260   case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2261   case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2279     Entry.IsSExt = isSigned;
2280     Entry.IsZExt = !isSigned;
2288   Entry.IsSExt = isSigned;
2289   Entry.IsZExt = !isSigned;
2301       .setSExtResult(isSigned)
2302       .setZExtResult(!isSigned);
2645   bool isSigned = (Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
2668     if (isSigned) {
2697         isSigned ? llvm::bit_cast<double>(0x4330000080000000ULL)
2723   if (isSigned)
3778     bool isSigned = Node->getOpcode() == ISD::SDIV;
3779     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;