Lines Matching +full:clear +full:- +full:bit
1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
41 #define DEBUG_TYPE "function-lowering-info"
43 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
47 if (I->use_empty()) return false;
49 const BasicBlock *BB = I->getParent();
50 for (const User *U : I->users())
51 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
67 for (const Use &U : I->uses()) {
69 NumOfSigned += CI->isSigned();
70 NumOfUnsigned += CI->isUnsigned();
73 if (!CallI->isArgOperand(&U))
75 unsigned ArgNo = CallI->getArgOperandNo(&U);
76 NumOfUnsigned += CallI->paramHasAttr(ArgNo, Attribute::ZExt);
77 NumOfSigned += CallI->paramHasAttr(ArgNo, Attribute::SExt);
90 TLI = MF->getSubtarget().getTargetLowering();
91 RegInfo = &MF->getRegInfo();
92 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
93 UA = DAG->getUniformityInfo();
95 // Check whether the function can return without sret-demotion.
97 CallingConv::ID CC = Fn->getCallingConv();
99 GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
102 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
104 // If this personality uses funclets, we need to do a bit more work.
107 Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
110 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
122 CatchObjects.insert({AI, {}}).first->second.push_back(
133 const Align StackAlign = TFI->getStackAlign();
137 Type *Ty = AI->getAllocatedType();
138 Align Alignment = AI->getAlign();
143 if (AI->isStaticAlloca() &&
144 (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
145 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
147 MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinValue();
149 TySize *= CUI->getZExtValue(); // Get total allocated size.
150 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
153 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
154 FrameIndex = MF->getFrameInfo().CreateFixedObject(
156 MF->getFrameInfo().setObjectAlignment(FrameIndex, Alignment);
158 FrameIndex = MF->getFrameInfo().CreateStackObject(TySize, Alignment,
165 if (Ty->isScalableTy())
166 MF->getFrameInfo().setStackID(FrameIndex,
167 TFI->getStackIDForScalableVectors());
172 for (int *CatchObjPtr : Iter->second)
179 // Inform the Frame Information that we have variable-sized objects.
180 MF->getFrameInfo().CreateVariableSizedObject(
185 if (Call->isInlineAsm()) {
186 Register SP = TLI->getStackPointerRegisterToSaveRestore();
187 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
189 TLI->ParseConstraints(Fn->getDataLayout(), TRI,
194 TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
196 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
199 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
207 if (II->getIntrinsicID() == Intrinsic::vastart)
208 MF->getFrameInfo().setHasVAStart(true);
214 if (CI->isMustTailCall() && Fn->isVarArg())
215 MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
219 if (Call->hasFnAttr(Attribute::ReturnsTwice))
220 MF->setExposesReturnsTwice(true);
231 if (DAG->getOptLevel() != CodeGenOptLevel::None)
244 // If this is a non-landingpad EH pad, mark this function as using
249 MF->setHasEHScopes(true);
250 MF->setHasEHFunclets(true);
251 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
265 MF->push_back(MBB);
267 // Transfer the address-taken flag. This is necessary because there could
271 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
275 MBB->setIsEHPad();
284 if (PN.getType()->isEmptyTy())
292 ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
294 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
295 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
297 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
304 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
325 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
348 /// clear - Clear out all the function-specific state. This returns this
351 void FunctionLoweringInfo::clear() {
352 MBBMap.clear();
353 ValueMap.clear();
354 VirtReg2Value.clear();
355 StaticAllocaMap.clear();
356 LiveOutRegInfo.clear();
357 VisitedBBs.clear();
358 ArgDbgValues.clear();
359 DescribedArgs.clear();
360 ByValArgFrameIndexMap.clear();
361 RegFixups.clear();
362 RegsWithFixups.clear();
363 StatepointStackSlots.clear();
364 StatepointRelocationMaps.clear();
365 PreferredExtendType.clear();
366 PreprocessedDbgDeclares.clear();
367 PreprocessedDVRDeclares.clear();
370 /// CreateReg - Allocate a single virtual register for the given type.
372 return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT, isDivergent));
375 /// CreateRegs - Allocate the appropriate number of virtual registers of
384 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
388 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
390 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
400 return CreateRegs(V->getType(), UA && UA->isDivergent(V) &&
401 !TLI->requiresUniformRegister(*MF, V));
406 if (V->getType()->isTokenTy() && !isa<ConvergenceControlInst>(V))
414 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
416 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
417 /// the larger bit width by zero extension. The bit width must be no smaller
418 /// than the LiveOutInfo's existing bit width.
425 if (!LOI->IsValid)
428 if (BitWidth > LOI->Known.getBitWidth()) {
429 LOI->NumSignBits = 1;
430 LOI->Known = LOI->Known.anyext(BitWidth);
436 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
439 Type *Ty = PN->getType();
440 if (!Ty->isIntegerTy() || Ty->isVectorTy())
444 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
446 "PHIs with non-vector integer types should have a single VT.");
449 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
451 IntVT = TLI->getRegisterType(PN->getContext(), IntVT);
458 Register DestReg = It->second;
465 Value *V = PN->getIncomingValue(0);
474 if (TLI->signExtendConstant(CI))
475 Val = CI->getValue().sext(BitWidth);
477 Val = CI->getValue().zext(BitWidth);
498 "Masks should have the same bit width as the type.");
500 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
501 Value *V = PN->getIncomingValue(i);
510 if (TLI->signExtendConstant(CI))
511 Val = CI->getValue().sext(BitWidth);
513 Val = CI->getValue().zext(BitWidth);
532 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
533 DestLOI.Known = DestLOI.Known.intersectWith(SrcLOI->Known);
537 /// setArgumentFrameIndex - Record frame index for the byval
545 /// getArgumentFrameIndex - Get frame index for the byval argument.
551 return I->second;
558 MachineRegisterInfo &MRI = MF->getRegInfo();
560 Register &VReg = I.first->second;
572 ValueVTs.clear();
573 ComputeValueVTs(*TLI, Fn->getDataLayout(),
574 P.first->getType(), ValueVTs);
577 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);