Lines Matching defs:Op0
485 Register Op0 = getRegForValue(I->getOperand(0));
486 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
507 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm,
523 ISDOpcode, Op0, Op1);
1542 Register Op0 = getRegForValue(I->getOperand(0));
1543 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1548 updateValueMap(I, Op0);
1553 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0);
1780 const Value *Op0 = EVI->getOperand(0);
1781 Type *AggTy = Op0->getType();
1785 DenseMap<const Value *, Register>::iterator I = FuncInfo.ValueMap.find(Op0);
1788 else if (isa<Instruction>(Op0))
1789 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1958 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/) {
1962 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1976 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1985 Register FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
2004 Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm);
2017 return fastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
2051 const TargetRegisterClass *RC, unsigned Op0) {
2055 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2059 .addReg(Op0);
2062 .addReg(Op0);
2072 const TargetRegisterClass *RC, unsigned Op0,
2077 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2082 .addReg(Op0)
2086 .addReg(Op0)
2096 const TargetRegisterClass *RC, unsigned Op0,
2101 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2107 .addReg(Op0)
2112 .addReg(Op0)
2123 const TargetRegisterClass *RC, unsigned Op0,
2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2132 .addReg(Op0)
2136 .addReg(Op0)
2146 const TargetRegisterClass *RC, unsigned Op0,
2151 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2155 .addReg(Op0)
2160 .addReg(Op0)
2191 const TargetRegisterClass *RC, unsigned Op0,
2196 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
2201 .addReg(Op0)
2206 .addReg(Op0)
2233 Register FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
2236 assert(Register::isVirtualRegister(Op0) &&
2238 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
2239 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
2241 ResultReg).addReg(Op0, 0, Idx);
2247 Register FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0) {
2248 return fastEmit_ri(VT, VT, ISD::AND, Op0, 1);