Lines Matching defs:SRL
1593 else if (Opc == ISD::SRL)
1887 case ISD::SRL: return visitSRL(N);
2036 case ISD::SRL:
2452 BinOpcode == ISD::SRL) && Sel.hasOneUse()) {
2597 ShiftOp.getOpcode() != ISD::SRL)
2618 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT,
3840 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3843 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
4070 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
4814 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
4920 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4936 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
5008 if ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) &&
5106 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
5154 hasOperation(ISD::SRL, VT)) {
5161 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
5176 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
5228 return DAG.getNode(ISD::SRL, DL, VT, X,
5387 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
5440 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
5830 // For binops SHL/SRL/SRA/AND:
5832 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
6383 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
6728 InnerShift = ISD::SRL;
6729 else if (OuterShift == ISD::SRL)
6788 if (Src.getOpcode() != ISD::SRL || !Src.hasOneUse())
6872 !(ShiftOpcode == ISD::SHL || ShiftOpcode == ISD::SRL ||
7370 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
7397 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
7399 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
7440 // Make sure everything beyond the low halfword gets set to zero since the SRL
7465 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
7482 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
7487 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
7491 // SHL or SRL: look upstream for AND mask operand
7508 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
7522 if (Opc0 != ISD::SRL)
7544 } else { // Opc == ISD::SRL
7567 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
7603 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
7684 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
7808 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL &&
8031 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
8066 if (OppShift.getOpcode() != ISD::SHL && OppShift.getOpcode() != ISD::SRL)
8080 if (OppShift.getOpcode() == ISD::SRL && OppShiftCst &&
8105 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) &&
8106 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
8362 if (IsBinOpImm(N1, ISD::SRL, 1) &&
8477 if (LHSShift.getOpcode() != ISD::SHL || RHSShift.getOpcode() != ISD::SRL)
8498 SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt);
8547 SDValue SrlY = DAG.getNode(ISD::SRL, DL, VT, Y, RHSShiftAmt);
8950 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) &&
9734 BinOpLHSVal.getOpcode() == ISD::SRL) &&
9989 N0.getOperand(0).getOpcode() == ISD::SRL) {
10010 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) {
10042 if (N0.getOpcode() == ISD::SRL &&
10052 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, Diff);
10053 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10175 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
10176 "SRL or SRA node is required here!");
10204 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) {
10409 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
10475 (N0.getOperand(0).getOpcode() == ISD::SRL ||
10499 // If the sign bit is known to be zero, switch this to a SRL.
10501 return DAG.getNode(ISD::SRL, DL, VT, N0, N1);
10531 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, DL, VT, {N0, N1}))
10549 if (N0.getOpcode() == ISD::SRL) {
10569 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum);
10574 N0.getOperand(0).getOpcode() == ISD::SRL) {
10589 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT,
10598 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT,
10627 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N01);
10638 Mask = DAG.getNode(ISD::SRL, DL, VT, Mask, N1);
10639 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10653 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
10657 DAG.getNode(ISD::SRL, DL0, SmallVT, N0.getOperand(0),
10671 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
10693 // could be set on input to the CTLZ node. If this bit is set, the SRL
10694 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
10695 // to an SRL/XOR pair, which is likely to simplify more.
10701 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
10713 return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
10743 // However when after the source operand of SRL is optimized into AND, the SRL
10814 ISD::SRL, DL, VT, N1,
10868 return DAG.getNode(ISD::SRL, DL, VT, N1, N2);
11072 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
11078 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL;
11110 if ((!LegalOperations || TLI.isOperationLegal(ISD::SRL, VT)) &&
11112 return DAG.getNode(ISD::SRL, DL, VT, X, Y);
11187 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SHL) {
11192 if ((N0.getOpcode() == ISD::SRL &&
12682 (B.getOpcode() == ISD::SRL || B.getOpcode() == ISD::SHL) &&
12752 if (NewShiftOpc == ISD::SHL || NewShiftOpc == ISD::SRL) {
13147 if (!(N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::SRL) ||
13433 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
14110 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
14450 } else if (Opc == ISD::SRL || Opc == ISD::SRA) {
14451 // Another special-case: SRL/SRA is basically zero/sign-extending a narrower
14467 // Attempt to fold away the SRL by using ZEXTLOAD and SRA by using SEXTLOAD.
14468 ExtType = Opc == ISD::SRL ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
14498 // In case Opc==SRL we've already prepared ExtVT/ExtType/ShAmt based on doing
14503 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) {
14504 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0;
14505 // Bail out when the SRL has more than one use. This is done for historical
14508 // case the SRL has multiple uses and we get here with Opc!=ISD::SRL?
14509 // FIXME: Can't we just skip this check for the Opc==ISD::SRL case.
14510 if (!SRL.hasOneUse())
14515 auto *LN = dyn_cast<LoadSDNode>(SRL.getOperand(0));
14516 auto *SRL1C = dyn_cast<ConstantSDNode>(SRL.getOperand(1));
14528 // Because a SRL must be assumed to *need* to zero-extend the high bits
14530 // lowering of SRL and an sextload.
14548 // If the SRL is only used by a masking AND, we may be able to adjust
14550 SDNode *Mask = *(SRL->use_begin());
14551 if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND &&
14560 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT))
14569 TLI.isLoadExtLegal(ExtType, SRL.getValueType(), MaskedVT)) {
14577 N0 = SRL.getOperand(0);
14753 if (N0.getOpcode() == ISD::SRL) {
14756 // We can turn this into an SRA iff the input to the SRL is already sign
15538 X = DAG.getNode(ISD::SRL, DL,
15644 // We currently avoid folding freeze over SRA/SRL, due to the problems seen
15645 // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
15647 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
18276 if (N.getOpcode() == ISD::SRL ||
18279 N.getOperand(0).getOpcode() == ISD::SRL))) {
18299 // SRL constant is equal to the log2 of the AND constant. The back-end is
19018 TLI.isOperationLegal(ISD::SRL, STType)) {
19019 Val = DAG.getNode(ISD::SRL, SDLoc(LD), STType, Val,
19663 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
19845 ISD::SRL, DL, IVal.getValueType(), IVal,
22480 case ISD::SRL:
23046 if (In.getOpcode() != ISD::SRL) {
23054 // In is SRL
27472 SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt);