Lines Matching defs:SRA
1591 if (Opc == ISD::SRA)
1886 case ISD::SRA: return visitSRA(N);
2035 case ISD::SRA:
2451 if ((BinOpcode == ISD::SHL || BinOpcode == ISD::SRA ||
2618 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT,
3840 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3843 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
4074 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
4075 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
4809 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
4818 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
5088 ISD::SRA, DL, VT, N0,
5225 return DAG.getNode(ISD::SRA, DL, VT, X,
5830 // For binops SHL/SRL/SRA/AND:
5833 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
6873 ShiftOpcode == ISD::SRA))
8950 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) &&
9550 SDValue S = N0Opcode == ISD::SRA ? N0 : N1;
9551 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
9733 BinOpLHSVal.getOpcode() == ISD::SRA ||
10010 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) {
10070 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
10175 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
10176 "SRL or SRA node is required here!");
10204 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) {
10279 bool IsSigned = N->getOpcode() == ISD::SRA;
10330 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, DL, VT, {N0, N1}))
10351 if (N0.getOpcode() == ISD::SRA) {
10377 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue);
10467 return DAG.getNode(ISD::SRA, DL, VT, N0, NewOp1);
10476 N0.getOperand(0).getOpcode() == ISD::SRA) &&
10488 SDValue SRA =
10489 DAG.getNode(ISD::SRA, DL, LargeVT, N0Op0.getOperand(0), Amt);
10490 return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA);
10670 if (N0.getOpcode() == ISD::SRA)
11346 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
11352 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
11564 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt);
11572 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt);
11583 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt);
12340 ISD::SRA, DL, VT, LHS,
12578 if (hasOperation(ISD::SRA, VT))
13433 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
14450 } else if (Opc == ISD::SRL || Opc == ISD::SRA) {
14451 // Another special-case: SRL/SRA is basically zero/sign-extending a narrower
14467 // Attempt to fold away the SRL by using ZEXTLOAD and SRA by using SEXTLOAD.
14756 // We can turn this into an SRA iff the input to the SRL is already sign
14760 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
15644 // We currently avoid folding freeze over SRA/SRL, due to the problems seen
15645 // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
15647 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
22478 // TODO: support ISD::SRA
27492 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt);
27712 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
27807 ISD::SRA, DL, CmpOpVT, N0,