Lines Matching defs:N00
1201 SDValue N00 = N0.getOperand(0);
1213 return DAG.getNode(Opc, DL, VT, N00, OpNode, NewFlags);
1219 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags);
1226 // (N00 & N01) & N00 --> N00 & N01
1227 // (N00 & N01) & N01 --> N00 & N01
1228 // (N00 | N01) | N00 --> N00 | N01
1229 // (N00 | N01) | N01 --> N00 | N01
1230 if (N1 == N00 || N1 == N01)
1234 // (N00 ^ N01) ^ N00 --> N01
1235 if (N1 == N00)
1237 // (N00 ^ N01) ^ N01 --> N00
1239 return N00;
1244 // Reassociate if (op N00, N1) already exist
1245 if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N00, N1})) {
1246 // if Op (Op N00, N1), N01 already exist
1253 if (N1 != N00) {
1256 // if Op (Op N01, N1), N00 already exist
1258 if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N00}))
1259 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N00);
1263 // Reassociate the operands from (OR/AND (OR/AND(N00, N001)), N1) to (OR/AND
1264 // (OR/AND(N00, N1)), N01) when N00 and N1 are comparisons with the same
1265 // predicate or to (OR/AND (OR/AND(N1, N01)), N00) when N01 and N1 are
1271 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC &&
1274 ISD::CondCode CC00 = cast<CondCodeSDNode>(N00.getOperand(2))->get();
1277 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, Flags);
1282 return DAG.getNode(Opc, DL, VT, OpNode, N00, Flags);
2674 SDValue N00 = N0.getOperand(0);
2682 if (SDValue Add = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N00}))
3921 SDValue N00 = N0.getOperand(0);
3922 if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N00, N1}))
5560 SDValue N00, N01, N02, N03;
5565 N00 = N02 = N0.getOperand(0);
5570 N00 = N0.getOperand(0);
5580 N00 = N0.getOperand(0).getOperand(0);
5590 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC);
7412 SDValue N00 = N0->getOperand(0);
7413 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
7414 if (!N00->hasOneUse())
7416 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
7419 N00 = N00.getOperand(0);
7437 if (N00 != N10)
7462 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
7658 SDValue N00 = N0.getOperand(0);
7660 if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) &&
7661 !(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts)))
7755 SDValue N00 = N0Resized.getOperand(0);
7759 if (N00 == N1Resized || N01 == N1Resized)
7764 if (SDValue NotOperand = getBitwiseNotOperand(N01, N00,
7767 return DAG.getNode(ISD::OR, DL, VT, DAG.getZExtOrTrunc(N00, DL, VT),
7772 if (SDValue NotOperand = getBitwiseNotOperand(N00, N01,
9502 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9503 if (isOneUseSetCC(N01) || isOneUseSetCC(N00)) {
9505 N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00
9507 AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode());
9508 return DAG.getNode(NewOpcode, DL, VT, N00, N01);
9514 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9515 if (isa<ConstantSDNode>(N01) || isa<ConstantSDNode>(N00)) {
9517 N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00
9519 AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode());
9520 return DAG.getNode(NewOpcode, DL, VT, N00, N01);
9762 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
9769 SDValue N00 = N->getOperand(0).getOperand(0);
9770 SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00);
9886 SDValue N00 = N0->getOperand(0);
9890 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
9891 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
9895 return DAG.getNode(ISD::AND, DL, VT, N00, C);
13445 SDValue N00 = N0.getOperand(0);
13449 EVT N00VT = N00.getValueType();
13471 return DAG.getSetCC(DL, VT, N00, N01, CC);
13478 SDValue VsetCC = DAG.getSetCC(DL, MatchingVecType, N00, N01, CC);
13522 if (IsFreeToExtend(N00) && IsFreeToExtend(N01)) {
13523 SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00);
13546 if (SDValue SCC = SimplifySelectCC(DL, N00, N01, ExtTrueVal, Zero, CC, true))
13557 SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC);
13595 SDValue N00 = N0.getOperand(0);
13597 if ((N00.getOpcode() == ISD::TRUNCATE || TLI.isTruncateFree(N00, ExtVT)) &&
13599 SDValue T = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N00);
14701 SDValue N00 = N0.getOperand(0);
14702 unsigned N00Bits = N00.getScalarValueSizeInBits();
14704 DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits) &&
14706 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00);
14713 SDValue N00 = N0.getOperand(0);
14714 unsigned N00Bits = N00.getScalarValueSizeInBits();
14716 unsigned SrcElts = N00.getValueType().getVectorMinNumElements();
14721 DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits))) &&
14724 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00);
14730 SDValue N00 = N0.getOperand(0);
14731 if (N00.getScalarValueSizeInBits() == ExtVTBits &&
14733 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00);
15187 SDValue N00 = N0.getOperand(0);
15188 if (N00.getOpcode() == ISD::SIGN_EXTEND ||
15189 N00.getOpcode() == ISD::ZERO_EXTEND ||
15190 N00.getOpcode() == ISD::ANY_EXTEND) {
15191 if (N00.getOperand(0)->getValueType(0).getVectorElementType() ==
15194 N00.getOperand(0), N0.getOperand(1));
15979 SDValue N00 = N0.getOperand(0);
15980 if (isContractableFMUL(N00) &&
15982 N00.getValueType())) {
15985 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)),
15986 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), N1);
16046 SDValue N00 = N0.getOperand(0);
16047 if (isFusedOp(N00)) {
16048 SDValue N002 = N00.getOperand(2);
16051 N00.getValueType())) {
16052 return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1),
16192 SDValue N00 = N0.getOperand(0).getOperand(0);
16195 matcher.getNode(ISD::FNEG, SL, VT, N00), N01,
16204 SDValue N00 = N0.getOperand(0);
16205 if (isContractableFMUL(N00) &&
16207 N00.getValueType())) {
16210 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)),
16211 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)),
16240 SDValue N00 = N0.getOperand(0);
16241 if (matcher.match(N00, ISD::FNEG)) {
16242 SDValue N000 = N00.getOperand(0);
16245 N00.getValueType())) {
16264 SDValue N00 = N0.getOperand(0);
16265 if (matcher.match(N00, ISD::FP_EXTEND)) {
16266 SDValue N000 = N00.getOperand(0);
16352 SDValue N00 = N0.getOperand(0);
16353 if (isFusedOp(N00)) {
16354 SDValue N002 = N00.getOperand(2);
16357 N00.getValueType())) {
16360 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)),
16361 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)),
16977 SDValue N00 = N0.getOperand(0);
16979 // Avoid an infinite loop by making sure that N00 is not a constant
16982 !DAG.isConstantFPBuildVectorOrConstantFP(N00)) {
16984 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts);
25402 SDValue N00 = N0.getOperand(0);
25406 unsigned ExtSrcSizeInBits = N00.getScalarValueSizeInBits();
25436 return DAG.getBitcast(VT, N00);