Lines Matching defs:N0
424 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
430 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
436 SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
438 SDValue visitSADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
447 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
449 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
460 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
462 SDValue visitORLike(SDValue N0, SDValue N1, const SDLoc &DL);
573 SDValue N0,
575 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
577 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
580 EVT VT, SDValue N0, SDValue N1,
590 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
591 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
595 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
598 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
602 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
608 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
637 SDValue buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N);
650 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
652 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
657 SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg,
1003 SDValue N0, N1, N2;
1004 if (isSetCCEquivalent(N, N0, N1, N2) && N->hasOneUse())
1075 SDValue N0,
1086 if (N0.getOpcode() != ISD::ADD)
1134 if (auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1135 if (N0.hasOneUse())
1165 if (auto *GA = dyn_cast<GlobalAddressSDNode>(N0.getOperand(1)))
1191 /// Helper for DAGCombiner::reassociateOps. Try to reassociate (Opc N0, N1) if
1192 /// \p N0 is the same kind of operation as \p Opc.
1194 SDValue N0, SDValue N1,
1196 EVT VT = N0.getValueType();
1198 if (N0.getOpcode() != Opc)
1201 SDValue N00 = N0.getOperand(0);
1202 SDValue N01 = N0.getOperand(1);
1206 if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() &&
1216 if (TLI.isReassocProfitable(DAG, N0, N1)) {
1219 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags);
1231 return N0;
1242 if (TLI.isReassocProfitable(DAG, N0, N1)) {
1277 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, Flags);
1281 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N01, N1, Flags);
1291 /// Try to reassociate commutative (Opc N0, N1) if either \p N0 or \p N1 is the
1293 SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
1298 if (N0.getValueType().isFloatingPoint() ||
1303 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1, Flags))
1305 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0, Flags))
1314 const SDLoc &DL, EVT VT, SDValue N0,
1316 if (N0.getOpcode() == RedOpc && N1.getOpcode() == RedOpc &&
1317 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
1318 N0->hasOneUse() && N1->hasOneUse() &&
1319 TLI.isOperationLegalOrCustom(Opc, N0.getOperand(0).getValueType()) &&
1320 TLI.shouldReassociateReduction(RedOpc, N0.getOperand(0).getValueType())) {
1323 DAG.getNode(Opc, DL, N0.getOperand(0).getValueType(),
1324 N0.getOperand(0), N1.getOperand(0)));
1522 SDValue N0 = Op.getOperand(0);
1523 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1533 // We are always replacing N0/N1's use in N and only need additional
1538 Replace0 &= !N0->hasOneUse();
1539 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1546 if (Replace0 && Replace1 && N0->isPredecessorOf(N1.getNode())) {
1547 std::swap(N0, N1);
1553 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1590 SDValue N0 = Op.getOperand(0);
1592 N0 = SExtPromoteOperand(N0, PVT);
1594 N0 = ZExtPromoteOperand(N0, PVT);
1596 N0 = PromoteOperand(N0, PVT, Replace);
1598 if (!N0.getNode())
1604 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1607 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
2054 SDValue N0 = N->getOperand(0);
2058 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
2059 SDValue Ops[] = {N1, N0};
2387 SDValue N0 = N->getOperand(0);
2390 std::swap(N0, N1);
2407 // This transform increases uses of N0, so freeze it to be safe.
2408 // binop N0, (vselect Cond, IDC, FVal) --> vselect Cond, N0, (binop N0, FVal)
2411 SDValue F0 = DAG.getFreeze(N0);
2415 // binop N0, (vselect Cond, TVal, IDC) --> vselect Cond, (binop N0, TVal), N0
2417 SDValue F0 = DAG.getFreeze(N0);
2565 SDValue N0 = N->getOperand(0);
2566 EVT VT = N0.getValueType();
2636 SDValue N0 = N->getOperand(0);
2638 EVT VT = N0.getValueType();
2642 if (N0.isUndef())
2643 return N0;
2648 if (SDValue C = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1}))
2652 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2654 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2656 if (areBitwiseNotOfEachother(N0, N1))
2666 return N0;
2671 return N0;
2673 if (N0.getOpcode() == ISD::SUB) {
2674 SDValue N00 = N0.getOperand(0);
2675 SDValue N01 = N0.getOperand(1);
2679 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
2683 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2690 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2692 SDValue X = N0.getOperand(0);
2706 if (DAG.isADDLike(N0)) {
2707 SDValue N01 = N0.getOperand(1);
2709 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add);
2716 if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N, N0, N1)) {
2717 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2726 auto ReassociateAddOr = [&](SDValue N0, SDValue N1) {
2727 if (DAG.isADDLike(N0) && N0.hasOneUse() &&
2728 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
2729 // If N0's type does not split or is a sign mask, it does not introduce
2731 auto TyActn = TLI.getTypeAction(*DAG.getContext(), N0.getValueType());
2734 isMinSignedConstant(N0.getOperand(1));
2738 DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
2739 N0.getOperand(1));
2743 if (SDValue Add = ReassociateAddOr(N0, N1))
2745 if (SDValue Add = ReassociateAddOr(N1, N0))
2750 reassociateReduction(ISD::VECREDUCE_ADD, ISD::ADD, DL, VT, N0, N1))
2757 if (sd_match(N0, m_Neg(m_Value(A))))
2762 return DAG.getNode(ISD::SUB, DL, VT, N0, B);
2765 if (sd_match(N1, m_Sub(m_Value(B), m_Specific(N0))))
2769 if (sd_match(N0, m_Sub(m_Value(B), m_Specific(N1))))
2773 if (sd_match(N0, m_Sub(m_Value(A), m_Value(B))) &&
2778 if (sd_match(N0, m_Sub(m_Value(A), m_Value(B))) &&
2784 if (sd_match(N1, m_Sub(m_Value(B), m_Add(m_Specific(N0), m_Value(C)))))
2789 m_AnyOf(m_Add(m_Sub(m_Value(B), m_Specific(N0)), m_Value(C)),
2790 m_Sub(m_Sub(m_Value(B), m_Specific(N0)), m_Value(C)))))
2794 if (sd_match(N0, m_OneUse(m_Sub(m_Value(A), m_Value(B)))) &&
2798 DAG.getNode(ISD::ADD, SDLoc(N0), VT, A, C),
2802 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2807 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2809 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2810 N0.getOperand(1));
2818 if (isBitwiseNot(N0))
2820 N0.getOperand(0));
2823 if (N0.getOpcode() == ISD::ADD) {
2826 if (isBitwiseNot(N0.getOperand(0))) {
2827 A = N0.getOperand(1);
2828 Xor = N0.getOperand(0);
2829 } else if (isBitwiseNot(N0.getOperand(1))) {
2830 A = N0.getOperand(0);
2831 Xor = N0.getOperand(1);
2842 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD &&
2843 N0.hasOneUse() &&
2847 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT);
2848 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
2853 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
2855 SDValue Not = DAG.getNOT(DL, N0.getOperand(1), VT);
2856 return DAG.getNode(ISD::ADD, DL, VT, Not, N0.getOperand(0));
2864 if (sd_match(N0, m_OneUse(m_Mul(m_Add(m_Value(A), m_ConstInt(CA)),
2872 N0->getFlags().hasNoUnsignedWrap() &&
2873 N0.getOperand(0)->getFlags().hasNoUnsignedWrap()) {
2876 N0->getFlags().hasNoSignedWrap() &&
2877 N0.getOperand(0)->getFlags().hasNoSignedWrap())
2887 if (sd_match(N0, m_OneUse(m_Add(
2897 N0.getOperand(0) == B ? N0.getOperand(1) : N0.getOperand(0);
2899 N0->getFlags().hasNoUnsignedWrap() &&
2904 N0->getFlags().hasNoSignedWrap() &&
2919 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2922 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2930 SDValue N0 = N->getOperand(0);
2931 EVT VT = N0.getValueType();
2951 SDValue N0 = N->getOperand(0);
2953 EVT VT = N0.getValueType();
2971 DAG.haveNoCommonBitsSet(N0, N1)) {
2974 return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags);
2978 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
2979 const APInt &C0 = N0->getConstantOperandAPInt(0);
2985 if (N0.getOpcode() == ISD::ADD &&
2986 N0.getOperand(1).getOpcode() == ISD::VSCALE &&
2988 const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
2991 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS);
2995 if (N0.getOpcode() == ISD::STEP_VECTOR &&
2997 const APInt &C0 = N0->getConstantOperandAPInt(0);
3004 if (N0.getOpcode() == ISD::ADD &&
3005 N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR &&
3007 const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0);
3011 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), SV);
3019 SDValue N0 = N->getOperand(0);
3021 EVT VT = N0.getValueType();
3026 if (N0.isUndef() || N1.isUndef())
3030 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
3034 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3036 return DAG.getNode(Opcode, DL, VT, N1, N0);
3045 return N0;
3050 return N0;
3053 if (DAG.willNotOverflowAdd(IsSigned, N0, N1))
3054 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
3111 static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
3119 EVT VT = N0.getValueType();
3130 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
3131 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
3132 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N10);
3135 /// Helper for doing combines based on N0 and N1 being added to each other.
3136 SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
3138 EVT VT = N0.getValueType();
3144 return DAG.getNode(ISD::SUB, DL, VT, N0,
3147 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
3154 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD &&
3155 N0.hasOneUse() && isOneOrOneSplat(N0.getOperand(1)) &&
3157 (Level >= AfterLegalizeDAG || (!N0->getFlags().hasNoUnsignedWrap() &&
3158 !N0->getFlags().hasNoSignedWrap()))) {
3159 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT);
3163 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) {
3167 if (isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3168 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
3169 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
3173 if (isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
3174 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
3175 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
3180 if (N0.getOpcode() == ISD::MUL && N0.getOperand(0) == N1 &&
3181 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true) &&
3182 N0.hasOneUse()) {
3183 SDValue NewC = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1),
3185 return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), NewC);
3191 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
3192 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
3194 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
3204 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
3212 N0, N1.getOperand(0), N1.getOperand(2));
3218 DAG.getVTList(VT, Carry.getValueType()), N0,
3225 SDValue N0 = N->getOperand(0);
3227 EVT VT = N0.getValueType();
3232 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3236 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3239 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
3243 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
3247 if (DAG.computeOverflowForUnsignedAdd(N0, N1) == SelectionDAG::OFK_Never)
3248 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3297 SDValue N0 = N->getOperand(0);
3299 EVT VT = N0.getValueType();
3307 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3311 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3313 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
3317 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3320 if (DAG.willNotOverflowAdd(IsSigned, N0, N1))
3321 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3326 if (isBitwiseNot(N0) && isOneOrOneSplat(N1))
3328 DAG.getConstant(0, DL, VT), N0.getOperand(0));
3331 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
3333 DAG.getConstant(0, DL, VT), N0.getOperand(0));
3338 if (SDValue Combined = visitUADDOLike(N0, N1, N))
3341 if (SDValue Combined = visitUADDOLike(N1, N0, N))
3348 SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
3349 EVT VT = N0.getValueType();
3359 return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0, Y,
3366 return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0,
3373 SDValue N0 = N->getOperand(0);
3378 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3382 N1, N0, CarryIn);
3386 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
3392 SDValue N0 = N->getOperand(0);
3398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3401 return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn);
3407 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
3411 if (isNullConstant(N0) && isNullConstant(N1)) {
3412 EVT VT = N0.getValueType();
3421 if (SDValue Combined = visitUADDO_CARRYLike(N0, N1, CarryIn, N))
3424 if (SDValue Combined = visitUADDO_CARRYLike(N1, N0, CarryIn, N))
3432 SDValue Ops[] = {N1, N0, CarryIn};
3557 SDValue N0, SDValue N1, SDNode *N) {
3558 SDValue Carry0 = getAsCarry(TLI, N0);
3628 SDValue DAGCombiner::visitUADDO_CARRYLike(SDValue N0, SDValue N1,
3632 if (isBitwiseNot(N0))
3636 N0.getOperand(0), NotC);
3645 if ((N0.getOpcode() == ISD::ADD ||
3646 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
3647 N0.getValue(1) != CarryIn)) &&
3650 N0.getOperand(0), N0.getOperand(1), CarryIn);
3659 if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
3661 if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
3668 SDValue DAGCombiner::visitSADDO_CARRYLike(SDValue N0, SDValue N1,
3671 if (isBitwiseNot(N0)) {
3674 N0.getOperand(0), NotC);
3681 SDValue N0 = N->getOperand(0);
3687 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3690 return DAG.getNode(ISD::SADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn);
3696 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1);
3699 if (SDValue Combined = visitSADDO_CARRYLike(N0, N1, CarryIn, N))
3702 if (SDValue Combined = visitSADDO_CARRYLike(N1, N0, CarryIn, N))
3796 SDValue N0 = N->getOperand(0);
3798 EVT VT = N0.getValueType();
3810 if (PeekThroughFreeze(N0) == PeekThroughFreeze(N1))
3814 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1}))
3824 return N0;
3832 return DAG.getNode(ISD::ADD, DL, VT, N0,
3835 if (isNullOrNullSplat(N0)) {
3851 return N0;
3857 return N0;
3879 if (isAllOnesOrAllOnesSplat(N0))
3880 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
3884 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
3887 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
3891 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
3892 return N0.getOperand(1);
3895 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
3896 return N0.getOperand(0);
3899 if (N0.getOpcode() == ISD::ADD) {
3900 SDValue N01 = N0.getOperand(1);
3902 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
3908 if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11}))
3913 if (N0.getOpcode() == ISD::SUB) {
3914 SDValue N01 = N0.getOperand(1);
3916 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
3920 if (N0.getOpcode() == ISD::SUB) {
3921 SDValue N00 = N0.getOperand(0);
3923 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
3929 if (sd_match(N0, m_Add(m_Value(A), m_Add(m_Specific(N1), m_Value(C)))))
3933 if (sd_match(N0, m_Add(m_Value(A), m_Sub(m_Specific(N1), m_Value(C)))))
3937 if (sd_match(N0, m_Sub(m_Value(A), m_Sub(m_Value(B), m_Specific(N1)))))
3942 return DAG.getNode(ISD::ADD, DL, VT, N0,
3946 if (sd_match(N1, m_And(m_Specific(N0), m_Value(B))) &&
3948 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getNOT(DL, B, VT));
3952 return DAG.getNode(ISD::ADD, DL, VT, N0,
3956 if (N0.isUndef())
3957 return N0;
3971 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, DL))
3986 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
3992 if (!reassociationCanBreakAddressingModePattern(ISD::SUB, DL, N, N0, N1) &&
3993 N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
3994 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3995 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3996 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
4001 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
4006 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
4007 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
4008 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
4009 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
4012 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
4013 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
4014 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
4015 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
4026 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
4032 sd_match(N0, m_Xor(m_Specific(A), m_Specific(N1))))
4036 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
4051 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
4058 return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
4064 return DAG.getNode(ISD::ADD, DL, VT, N0,
4069 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
4075 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
4081 // N0 - (X << BW-1) --> N0 + (X << BW-1)
4085 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
4089 if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) &&
4090 N0.getResNo() == 0 && N0.hasOneUse())
4091 return DAG.getNode(ISD::USUBO_CARRY, DL, N0->getVTList(),
4092 N0.getOperand(0), N1, N0.getOperand(2));
4096 if (SDValue Carry = getAsCarry(TLI, N0)) {
4108 if (ConstantSDNode *C0 = isConstOrConstSplat(N0)) {
4113 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
4119 sd_match(N0, m_SMax(m_Value(A), m_Value(B))) &&
4125 sd_match(N0, m_UMax(m_Value(A), m_Value(B))) &&
4134 SDValue N0 = N->getOperand(0);
4136 EVT VT = N0.getValueType();
4141 if (N0.isUndef() || N1.isUndef())
4145 if (N0 == N1)
4149 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
4159 return N0;
4164 return N0;
4167 if (DAG.willNotOverflowSub(IsSigned, N0, N1))
4168 return DAG.getNode(ISD::SUB, DL, VT, N0, N1);
4174 SDValue N0 = N->getOperand(0);
4176 EVT VT = N0.getValueType();
4181 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
4185 if (N0 == N1)
4191 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
4194 if (isAllOnesConstant(N0))
4195 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
4202 SDValue N0 = N->getOperand(0);
4204 EVT VT = N0.getValueType();
4212 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
4216 if (N0 == N1)
4223 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
4228 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
4231 if (DAG.willNotOverflowSub(IsSigned, N0, N1))
4232 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
4236 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
4237 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
4244 SDValue N0 = N->getOperand(0);
4250 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
4256 SDValue N0 = N->getOperand(0);
4264 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
4271 SDValue N0 = N->getOperand(0);
4279 return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1);
4288 SDValue N0 = N->getOperand(0);
4291 EVT VT = N0.getValueType();
4294 if (N0.isUndef() || N1.isUndef())
4298 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4300 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
4310 SDValue N0 = N->getOperand(0);
4312 EVT VT = N0.getValueType();
4319 if (N0.isUndef() || N1.isUndef())
4323 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, DL, VT, {N0, N1}))
4327 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4329 return Matcher.getNode(ISD::MUL, DL, VT, N1, N0);
4359 return N0;
4367 return Matcher.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
4373 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4375 return Matcher.getNode(ISD::SHL, DL, VT, N0, Trunc);
4387 Matcher.getNode(ISD::SHL, DL, VT, N0,
4398 if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N0, N1}))
4401 if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N1, N0}))
4445 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
4448 DAG.getNode(ISD::SHL, DL, VT, N0,
4450 : DAG.getNode(MathOp, DL, VT, Shl, N0);
4458 if (sd_context_match(N0, Matcher, m_Opc(ISD::SHL))) {
4459 SDValue N01 = N0.getOperand(1);
4461 return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), C3);
4470 if (sd_context_match(N0, Matcher, m_OneUse(m_Opc(ISD::SHL))) &&
4471 isConstantOrConstantVector(N0.getOperand(1))) {
4472 Sh = N0; Y = N1;
4475 Sh = N1; Y = N0;
4485 if (sd_context_match(N0, Matcher, m_Opc(ISD::ADD)) &&
4487 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
4488 isMulAddWithConstProfitable(N, N0, N1))
4491 Matcher.getNode(ISD::MUL, SDLoc(N0), VT, N0.getOperand(0), N1),
4492 Matcher.getNode(ISD::MUL, SDLoc(N1), VT, N0.getOperand(1), N1));
4496 if (!UseVP && N0.getOpcode() == ISD::VSCALE && NC1) {
4497 const APInt &C0 = N0.getConstantOperandAPInt(0);
4504 if (!UseVP && N0.getOpcode() == ISD::STEP_VECTOR &&
4506 const APInt &C0 = N0.getConstantOperandAPInt(0);
4547 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getBuildVector(VT, DL, Mask));
4554 if (SDValue RMUL = reassociateOps(ISD::MUL, DL, N0, N1, N->getFlags()))
4561 reassociateReduction(ISD::VECREDUCE_MUL, ISD::MUL, DL, VT, N0, N1))
4660 SDValue N0 = N->getOperand(0);
4674 if (DAG.isUndef(Opc, {N0, N1}))
4679 if (N0.isUndef())
4684 ConstantSDNode *N0C = isConstOrConstSplat(N0);
4686 return N0;
4690 if (N0 == N1)
4700 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
4706 SDValue N0 = N->getOperand(0);
4713 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1}))
4724 return DAG.getNegative(N0, DL, VT);
4728 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4740 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4741 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
4743 if (SDValue V = visitSDIVLike(N0, N1, N)) {
4747 { N0, N1 })) {
4749 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4784 SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4800 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
4809 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
4813 // Add (N0 < 0) ? abs2 - 1 : 0;
4816 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
4828 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
4854 SDValue N0 = N->getOperand(0);
4861 if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1}))
4872 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4883 if (SDValue V = visitUDIVLike(N0, N1, N)) {
4887 { N0, N1 })) {
4889 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4908 SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4917 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4920 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4936 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
4951 SDValue DAGCombiner::buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N) {
4953 !DAG.doesNodeExist(ISD::SDIV, N->getVTList(), {N0, N1})) {
4964 SDValue N0 = N->getOperand(0);
4973 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
4980 SDValue F0 = DAG.getFreeze(N0);
4994 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4995 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
5002 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
5013 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
5029 if (SDValue OptimizedRem = buildOptimizedSREM(N0, N1, N))
5034 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
5039 { N0, N1 }))
5042 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
5057 SDValue N0 = N->getOperand(0);
5063 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHS, DL, VT, {N0, N1}))
5067 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5069 return DAG.getNode(ISD::MULHS, DL, N->getVTList(), N1, N0);
5088 ISD::SRA, DL, VT, N0,
5089 DAG.getShiftAmountConstant(N0.getScalarValueSizeInBits() - 1, VT, DL));
5092 if (N0.isUndef() || N1.isUndef())
5103 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
5105 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
5116 SDValue N0 = N->getOperand(0);
5122 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHU, DL, VT, {N0, N1}))
5126 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5128 return DAG.getNode(ISD::MULHU, DL, N->getVTList(), N1, N0);
5149 if (N0.isUndef() || N1.isUndef())
5159 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
5161 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
5173 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
5175 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
5193 SDValue N0 = N->getOperand(0);
5200 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
5204 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5206 return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0);
5213 if (N0.isUndef())
5216 return N0;
5219 if (N0 == N1 && Level >= AfterLegalizeTypes)
5220 return N0;
5255 ISD::AVGCEILU, DL, VT, N0,
5257 if (DAG.isKnownNeverZero(N0))
5260 DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getAllOnesConstant(DL, VT)));
5268 SDValue N0 = N->getOperand(0);
5274 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
5278 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5280 return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0);
5287 if (N0.isUndef() || N1.isUndef())
5303 DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
5304 return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
5362 SDValue N0 = N->getOperand(0);
5368 if (isa<ConstantSDNode>(N0) && isa<ConstantSDNode>(N1))
5369 return DAG.getNode(ISD::SMUL_LOHI, DL, N->getVTList(), N0, N1);
5372 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5374 return DAG.getNode(ISD::SMUL_LOHI, DL, N->getVTList(), N1, N0);
5383 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
5390 // Compute the low part as N0.
5403 SDValue N0 = N->getOperand(0);
5409 if (isa<ConstantSDNode>(N0) && isa<ConstantSDNode>(N1))
5410 return DAG.getNode(ISD::UMUL_LOHI, DL, N->getVTList(), N0, N1);
5413 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5415 return DAG.getNode(ISD::UMUL_LOHI, DL, N->getVTList(), N1, N0);
5417 // (umul_lohi N0, 0) -> (0, 0)
5423 // (umul_lohi N0, 1) -> (N0, 0)
5426 return CombineTo(N, N0, Zero);
5436 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
5443 // Compute the low part as N0.
5453 SDValue N0 = N->getOperand(0);
5455 EVT VT = N0.getValueType();
5461 ConstantSDNode *N0C = isConstOrConstSplat(N0);
5477 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5479 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
5491 N->getVTList(), N0, N0);
5495 SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, N1);
5502 if (DAG.willNotOverflowMul(IsSigned, N0, N1))
5503 return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1),
5513 // same as SimplifySelectCC. N0<N1 ? N2 : N3.
5514 static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2,
5517 auto isSignedMinMax = [&](SDValue N0, SDValue N1, SDValue N2, SDValue N3,
5521 if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0)))
5536 unsigned Opcode0 = isSignedMinMax(N0, N1, N2, N3, CC);
5542 if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) {
5544 EVT IntVT = N0.getValueType().getScalarType();
5545 EVT FPVT = N0.getOperand(0).getValueType().getScalarType();
5554 return N0;
5562 switch (N0.getOpcode()) {
5565 N00 = N02 = N0.getOperand(0);
5566 N01 = N03 = N0.getOperand(1);
5567 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT;
5570 N00 = N0.getOperand(0);
5571 N01 = N0.getOperand(1);
5572 N02 = N0.getOperand(2);
5573 N03 = N0.getOperand(3);
5574 N0CC = cast<CondCodeSDNode>(N0.getOperand(4))->get();
5578 if (N0.getOperand(0).getOpcode() != ISD::SETCC)
5580 N00 = N0.getOperand(0).getOperand(0);
5581 N01 = N0.getOperand(0).getOperand(1);
5582 N02 = N0.getOperand(1);
5583 N03 = N0.getOperand(2);
5584 N0CC = cast<CondCodeSDNode>(N0.getOperand(0).getOperand(2))->get();
5617 static SDValue PerformMinMaxFpToSatCombine(SDValue N0, SDValue N1, SDValue N2,
5622 SDValue Fp = isSaturatingMinMax(N0, N1, N2, N3, CC, BW, Unsigned, DAG);
5639 static SDValue PerformUMinFpToSatCombine(SDValue N0, SDValue N1, SDValue N2,
5644 // be truncated versions of the setcc (N0/N1).
5645 if ((N0 != N2 &&
5646 (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) ||
5647 N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT)
5660 EVT FPVT = N0.getOperand(0).getValueType();
5670 DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), NewVT, N0.getOperand(0),
5672 return DAG.getZExtOrTrunc(Sat, SDLoc(N0), N3.getValueType());
5676 SDValue N0 = N->getOperand(0);
5678 EVT VT = N0.getValueType();
5683 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
5687 if (N0 == N1)
5688 return N0;
5691 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5693 return DAG.getNode(Opcode, DL, VT, N1, N0);
5701 if (SDValue RMINMAX = reassociateOps(Opcode, DL, N0, N1, N->getFlags()))
5709 bool IsSatBroken = Opcode == ISD::UMIN && N0.getOpcode() == ISD::SMAX;
5710 if ((IsSatBroken || IsOpIllegal) && (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
5721 return DAG.getNode(AltOpcode, DL, VT, N0, N1);
5726 N0, N1, N0, N1, Opcode == ISD::SMIN ? ISD::SETLT : ISD::SETGT, DAG))
5729 if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N0, N1, ISD::SETULT, DAG))
5748 SDLoc(N), VT, N0, N1))
5761 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
5762 EVT VT = N0.getValueType();
5764 unsigned HandOpcode = N0.getOpcode();
5769 if (N0.getNumOperands() == 0)
5776 SDValue X = N0.getOperand(0);
5782 N0.getOperand(1) == N1.getOperand(1))) {
5785 if (!N0.hasOneUse() && !N1.hasOneUse())
5804 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
5812 if (!N0.hasOneUse() && !N1.hasOneUse())
5834 N0.getOperand(1) == N1.getOperand(1)) {
5836 if (!N0.hasOneUse() || !N1.hasOneUse())
5839 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
5845 if (!N0.hasOneUse() || !N1.hasOneUse())
5855 N0.getOperand(2) == N1.getOperand(2)) {
5856 if (!N0.hasOneUse() || !N1.hasOneUse())
5858 SDValue X1 = N0.getOperand(1);
5860 SDValue S = N0.getOperand(2);
5897 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
5912 SDValue ShOp = N0.getOperand(1);
5917 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
5919 N0.getOperand(0), N1.getOperand(0));
5925 ShOp = N0.getOperand(0);
5930 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
5931 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
5941 SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
5944 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
5948 assert(N0.getValueType() == N1.getValueType() &&
5957 EVT VT = N0.getValueType();
5986 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
6005 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
6019 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
6027 N0.hasOneUse() && N1.hasOneUse()) {
6031 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
6366 SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
6371 if (N0.isUndef() || N1.isUndef())
6374 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
6380 std::swap(N0, N1);
6383 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
6384 VT.isScalarInteger() && VT.getSizeInBits() <= 64 && N0->hasOneUse()) {
6385 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6397 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
6400 SDLoc DL0(N0);
6403 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
6404 CombineTo(N0.getNode(), NewAdd);
6712 SDValue N0 = N->getOperand(0);
6716 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
6741 X = N0;
6742 else if (matchMask(N0))
6940 SDValue N0 = N->getOperand(0);
6946 if (N0 == N1)
6947 return N0;
6950 if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, DL, VT, {N0, N1}))
6954 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
6956 return DAG.getNode(ISD::AND, DL, VT, N1, N0);
6958 if (areBitwiseNotOfEachother(N0, N1))
6974 return N0;
6977 auto *MLoad = dyn_cast<MaskedLoadSDNode>(N0);
6995 bool LoadHasOtherUsers = !N0.hasOneUse();
7007 return N0;
7022 if (SDValue RAND = reassociateOps(ISD::AND, DL, N0, N1, N->getFlags()))
7027 reassociateReduction(ISD::VECREDUCE_AND, ISD::AND, DL, VT, N0, N1))
7034 if (N0.getOpcode() == ISD::OR &&
7035 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
7038 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
7039 SDValue N0Op0 = N0.getOperand(0);
7060 if (ISD::isExtOpcode(N0.getOpcode())) {
7061 unsigned ExtOpc = N0.getOpcode();
7062 SDValue N0Op0 = N0.getOperand(0);
7067 N0->hasOneUse() && N0Op0->hasOneUse()) {
7083 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7084 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
7085 N0.getOperand(0).getOpcode() == ISD::LOAD &&
7086 N0.getOperand(0).getResNo() == 0) ||
7087 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
7089 cast<LoadSDNode>((N0.getOpcode() == ISD::LOAD) ? N0 : N0.getOperand(0));
7156 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
7184 if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
7187 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C &&
7188 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) {
7189 SDValue Ext = N0.getOperand(0);
7202 N0.getOperand(1));
7207 if (auto *GN0 = dyn_cast<MaskedGatherSDNode>(N0)) {
7230 if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector())
7243 if (SDValue Combined = visitANDLike(N0, N1, N))
7247 if (N0.getOpcode() == N1.getOpcode())
7251 if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG))
7253 if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG))
7263 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
7264 if (isNullOrNullSplat(N0.getOperand(0))) {
7265 SDValue SubRHS = N0.getOperand(1);
7282 if (ISD::isUNINDEXEDLoad(N0.getNode()) &&
7283 (ISD::isEXTLoad(N0.getNode()) ||
7284 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) {
7285 auto *LN0 = cast<LoadSDNode>(N0);
7296 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
7299 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
7305 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
7306 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
7307 N0.getOperand(1), false))
7339 if (IsAndZeroExtMask(N0, N1))
7340 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
7349 if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG))
7356 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
7370 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
7371 std::swap(N0, N1);
7373 std::swap(N0, N1);
7374 if (N0.getOpcode() == ISD::AND) {
7375 if (!N0->hasOneUse())
7377 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7383 N0 = N0.getOperand(0);
7397 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
7398 std::swap(N0, N1);
7399 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
7401 if (!N0->hasOneUse() || !N1->hasOneUse())
7404 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7412 SDValue N00 = N0->getOperand(0);
7485 SDValue N0 = N.getOperand(0);
7486 unsigned Opc0 = N0.getOpcode();
7495 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7524 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7532 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7557 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
7583 SelectionDAG &DAG, SDNode *N, SDValue N0,
7589 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
7592 if (!N0->hasOneUse() || !N1->hasOneUse())
7594 ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1));
7601 SDValue Shift0 = N0.getOperand(0);
7626 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
7636 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT))
7640 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT))
7650 if (isBSwapHWordPair(N0, Parts)) {
7654 } else if (N0.getOpcode() == ISD::OR) {
7658 SDValue N00 = N0.getOperand(0);
7659 SDValue N01 = N0.getOperand(1);
7689 SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, const SDLoc &DL) {
7693 if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
7696 if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
7700 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
7702 (N0->hasOneUse() || N1->hasOneUse())) {
7706 getAsNonOpaqueConstant(N0.getOperand(1))) {
7714 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
7716 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
7717 N0.getOperand(0), N1.getOperand(0));
7726 if (N0.getOpcode() == ISD::AND &&
7728 N0.getOperand(0) == N1.getOperand(0) &&
7730 (N0->hasOneUse() || N1->hasOneUse())) {
7731 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
7732 N0.getOperand(1), N1.getOperand(1));
7733 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
7740 static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1,
7742 EVT VT = N0.getValueType();
7752 SDValue N0Resized = peekThroughResize(N0);
7783 if (sd_match(N0, m_Xor(m_Value(X), m_Specific(N1))))
7787 if (sd_match(N0, m_Xor(m_Value(X), m_Value(Y))) &&
7792 if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG))
7802 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL &&
7803 N0.getOperand(0) == N1.getOperand(0) &&
7804 peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1)))
7805 return N0;
7808 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL &&
7809 N0.getOperand(1) == N1.getOperand(0) &&
7810 peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1)))
7811 return N0;
7816 if (sd_match(N0,
7837 SDValue N0 = N->getOperand(0);
7843 if (N0 == N1)
7844 return N0;
7847 if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, DL, VT, {N0, N1}))
7851 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
7853 return DAG.getNode(ISD::OR, DL, VT, N1, N0);
7862 return N0;
7871 auto *SV0 = dyn_cast<ShuffleVectorSDNode>(N0);
7874 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
7875 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
7915 SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
7928 return N0;
7939 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
7945 if (SDValue Combined = visitORLike(N0, N1, DL))
7948 if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
7952 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
7954 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
7958 if (SDValue ROR = reassociateOps(ISD::OR, DL, N0, N1, N->getFlags()))
7963 reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, DL, VT, N0, N1))
7971 if (N0.getOpcode() == ISD::AND && N0->hasOneUse() &&
7972 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) {
7974 {N1, N0.getOperand(1)})) {
7975 SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
7981 if (SDValue Combined = visitORCommutative(DAG, N0, N1, N))
7983 if (SDValue Combined = visitORCommutative(DAG, N1, N0, N))
7987 if (N0.getOpcode() == N1.getOpcode())
7992 if (SDValue Rot = MatchRotate(N0, N1, DL))
8011 if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG))
8324 // shifts of N0 + N1. If Neg == <operand size> - Pos then the OR reduces
8325 // to both (PosOpcode N0, N1, Pos) and (NegOpcode N0, N1, Neg), with the
8329 SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos,
8334 EVT VT = N0.getValueType();
8344 if (matchRotateSub(InnerPos, InnerNeg, EltBits, DAG, /*IsRotate*/ N0 == N1)) {
8345 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, N0, N1,
8366 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos);
8371 if (IsBinOpImm(N0, ISD::SHL, 1) &&
8375 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg);
8381 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) &&
8385 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg);
9336 SDValue N0 = N->getOperand(0);
9338 if (!matchAndXor(N0, 0, N1) && !matchAndXor(N0, 1, N1) &&
9339 !matchAndXor(N1, 0, N0) && !matchAndXor(N1, 1, N0))
9387 SDValue N0 = N->getOperand(0);
9389 EVT VT = N0.getValueType();
9393 if (N0.isUndef() && N1.isUndef())
9397 if (N0.isUndef())
9398 return N0;
9403 if (SDValue C = DAG.FoldConstantArithmetic(ISD::XOR, DL, VT, {N0, N1}))
9407 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
9409 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
9418 return N0;
9423 return N0;
9429 if (SDValue RXOR = reassociateOps(ISD::XOR, DL, N0, N1, N->getFlags()))
9434 reassociateReduction(ISD::VECREDUCE_XOR, ISD::XOR, DL, VT, N0, N1))
9439 DAG.haveNoCommonBitsSet(N0, N1)) {
9442 return DAG.getNode(ISD::OR, DL, VT, N0, N1, Flags);
9446 // XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE)
9453 unsigned N0Opcode = N0.getOpcode();
9456 isSetCCEquivalent(N0, LHS, RHS, CC, /*MatchStrict*/ true)) {
9465 return DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC);
9467 return DAG.getSelectCC(SDLoc(N0), LHS, RHS, N0.getOperand(2),
9468 N0.getOperand(3), NotCC);
9471 if (N0.hasOneUse()) {
9475 DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC,
9476 N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS);
9478 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1));
9479 recursivelyDeleteUnusedNodes(N0.getNode());
9489 if (isOneConstant(N1) && N0Opcode == ISD::ZERO_EXTEND && N0.hasOneUse() &&
9490 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
9491 SDValue V = N0.getOperand(0);
9492 SDLoc DL0(N0);
9500 if (isOneConstant(N1) && VT == MVT::i1 && N0.hasOneUse() &&
9502 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9512 if (isAllOnesConstant(N1) && N0.hasOneUse() &&
9514 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9527 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB &&
9528 isNullConstant(N0.getOperand(0))) {
9529 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1),
9534 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD &&
9535 isAllOnesOrAllOnesSplat(N0.getOperand(1))) {
9536 return DAG.getNegative(N0.getOperand(0), DL, VT);
9540 if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) {
9541 SDValue X = N0.getOperand(0);
9549 SDValue A = N0Opcode == ISD::ADD ? N0 : N1;
9550 SDValue S = N0Opcode == ISD::SRA ? N0 : N1;
9562 if (N0 == N1)
9584 isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) {
9586 N0.getOperand(1));
9594 if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG))
9596 if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG))
9598 if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG))
9609 if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
9783 SDValue N0 = N->getOperand(0);
9790 return N0;
9796 return N0;
9810 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt);
9817 return DAG.getNode(ISD::BSWAP, dl, VT, N0);
9827 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1);
9830 unsigned NextOp = N0.getOpcode();
9836 SDNode *C2 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1));
9845 {N0.getOperand(1), BitsizeC});
9853 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0),
9862 SDValue N0 = N->getOperand(0);
9864 if (SDValue V = DAG.simplifyShift(N0, N1))
9868 EVT VT = N0.getValueType();
9873 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, DL, VT, {N0, N1}))
9885 if (N0.getOpcode() == ISD::AND) {
9886 SDValue N00 = N0->getOperand(0);
9887 SDValue N01 = N0->getOperand(1);
9912 return DAG.getNode(ISD::SHL, DL, VT, N0, NewOp1);
9916 if (N0.getOpcode() == ISD::SHL) {
9924 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
9934 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
9935 SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
9936 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Sum);
9945 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
9946 N0.getOpcode() == ISD::ANY_EXTEND ||
9947 N0.getOpcode() == ISD::SIGN_EXTEND) &&
9948 N0.getOperand(0).getOpcode() == ISD::SHL) {
9949 SDValue N0Op0 = N0.getOperand(0);
9978 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0));
9988 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
9989 N0.getOperand(0).getOpcode() == ISD::SRL) {
9990 SDValue N0Op0 = N0.getOperand(0);
10006 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
10010 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) {
10021 if (N0->getFlags().hasExact()) {
10022 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount,
10025 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10027 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
10029 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
10032 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10034 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff);
10042 if (N0.getOpcode() == ISD::SRL &&
10043 (N0.getOperand(1) == N1 || N0.hasOneUse()) &&
10045 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
10048 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10053 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10056 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount,
10059 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10063 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
10070 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
10074 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask);
10081 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
10082 N0->hasOneUse() && TLI.isDesirableToCommuteWithShift(N, Level)) {
10083 SDValue N01 = N0.getOperand(1);
10086 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
10090 if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
10092 return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
10099 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
10100 N0.getOperand(0).getOpcode() == ISD::ADD &&
10101 N0.getOperand(0)->getFlags().hasNoSignedWrap() && N0->hasOneUse() &&
10102 N0.getOperand(0)->hasOneUse() &&
10104 SDValue Add = N0.getOperand(0);
10105 SDLoc DL(N0);
10106 if (SDValue ExtC = DAG.FoldConstantArithmetic(N0.getOpcode(), DL, VT,
10110 SDValue ExtX = DAG.getNode(N0.getOpcode(), DL, VT, Add.getOperand(0));
10118 if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) {
10119 SDValue N01 = N0.getOperand(1);
10122 return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), Shl);
10142 return DAG.getNode(ISD::MUL, DL, VT, And, N0);
10149 if (N0.getOpcode() == ISD::VSCALE && N1C) {
10150 const APInt &C0 = N0.getConstantOperandAPInt(0);
10157 if (N0.getOpcode() == ISD::STEP_VECTOR &&
10159 const APInt &C0 = N0.getConstantOperandAPInt(0);
10290 SDValue N0 = N->getOperand(0);
10293 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) {
10294 SDValue OldLHS = N0.getOperand(0);
10295 SDValue OldRHS = N0.getOperand(1);
10300 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0),
10306 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0),
10312 return DAG.getNode(N0.getOpcode(), DL, VT, NewBitReorder,
10320 SDValue N0 = N->getOperand(0);
10322 if (SDValue V = DAG.simplifyShift(N0, N1))
10326 EVT VT = N0.getValueType();
10330 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, DL, VT, {N0, N1}))
10336 if (DAG.ComputeNumSignBits(N0) == OpSizeInBits)
10337 return N0;
10351 if (N0.getOpcode() == ISD::SRA) {
10366 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), SumOfShifts)) {
10377 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue);
10386 if (N0.getOpcode() == ISD::SHL && N1C) {
10388 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
10410 N0.getOperand(0), Amt);
10424 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C &&
10425 N0.hasOneUse()) {
10426 bool IsAdd = N0.getOpcode() == ISD::ADD;
10427 SDValue Shl = N0.getOperand(IsAdd ? 0 : 1);
10432 isConstOrConstSplat(N0.getOperand(IsAdd ? 1 : 0))) {
10467 return DAG.getNode(ISD::SRA, DL, VT, N0, NewOp1);
10474 if (N0.getOpcode() == ISD::TRUNCATE &&
10475 (N0.getOperand(0).getOpcode() == ISD::SRL ||
10476 N0.getOperand(0).getOpcode() == ISD::SRA) &&
10477 N0.getOperand(0).hasOneUse() &&
10478 N0.getOperand(0).getOperand(1).hasOneUse() && N1C) {
10479 SDValue N0Op0 = N0.getOperand(0);
10500 if (DAG.SignBitIsZero(N0))
10501 return DAG.getNode(ISD::SRL, DL, VT, N0, N1);
10520 SDValue N0 = N->getOperand(0);
10522 if (SDValue V = DAG.simplifyShift(N0, N1))
10526 EVT VT = N0.getValueType();
10531 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, DL, VT, {N0, N1}))
10549 if (N0.getOpcode() == ISD::SRL) {
10557 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
10567 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
10568 SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
10569 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum);
10573 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
10574 N0.getOperand(0).getOpcode() == ISD::SRL) {
10575 SDValue InnerShift = N0.getOperand(0);
10595 if (N0.hasOneUse() && InnerShift.hasOneUse() &&
10611 if (N0.getOpcode() == ISD::SHL &&
10612 (N0.getOperand(1) == N1 || N0->hasOneUse()) &&
10621 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
10624 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10629 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
10632 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount,
10635 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10639 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10646 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
10648 EVT SmallVT = N0.getOperand(0).getValueType();
10655 SDLoc DL0(N0);
10657 DAG.getNode(ISD::SRL, DL0, SmallVT, N0.getOperand(0),
10670 if (N0.getOpcode() == ISD::SRA)
10671 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
10676 if (N1C && N0.getOpcode() == ISD::CTLZ &&
10679 KnownBits Known = DAG.computeKnownBits(N0.getOperand(0));
10683 if (Known.One.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
10688 if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
10697 SDValue Op = N0.getOperand(0);
10700 SDLoc DL(N0);
10713 return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
10775 SDValue N0 = N->getOperand(0);
10782 // fold (fshl N0, N1, 0) -> N0
10783 // fold (fshr N0, N1, 0) -> N1
10787 return IsFSHL ? N0 : N1;
10797 // fold (fsh* N0, N1, c) -> (fsh* N0, N1, c % BitWidth)
10800 return DAG.getNode(N->getOpcode(), DL, VT, N0, N1,
10806 return IsFSHL ? N0 : N1;
10810 // fold fshl(N0, undef_or_zero, C) -> shl(N0, C)
10811 // fold fshr(N0, undef_or_zero, C) -> shl(N0, BW-C)
10812 if (IsUndefOrZero(N0))
10818 ISD::SHL, DL, VT, N0,
10828 auto *LHS = dyn_cast<LoadSDNode>(N0);
10862 // fold fshl(N0, undef_or_zero, N2) -> shl(N0, N2)
10867 if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits))
10870 return DAG.getNode(ISD::SHL, DL, VT, N0, N2);
10873 // fold (fshl N0, N0, N2) -> (rotl N0, N2)
10874 // fold (fshr N0, N0, N2) -> (rotr N0, N2)
10879 if (N0 == N1 && hasOperation(RotOpc, VT))
10880 return DAG.getNode(RotOpc, DL, VT, N0, N2);
10882 // Simplify, based on bits shifted out of N0/N1.
10890 SDValue N0 = N->getOperand(0);
10892 if (SDValue V = DAG.simplifyShift(N0, N1))
10896 EVT VT = N0.getValueType();
10899 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
10907 N1C->getAPIntValue().ult(DAG.ComputeNumSignBits(N0)))
10908 return DAG.getNode(ISD::SHL, DL, VT, N0, N1);
10913 DAG.computeKnownBits(N0).countMinLeadingZeros()))
10914 return DAG.getNode(ISD::SHL, DL, VT, N0, N1);
10992 SDValue N0 = N->getOperand(0);
10997 if (SDValue C = DAG.FoldConstantArithmetic(ISD::ABS, DL, VT, {N0}))
11000 if (N0.getOpcode() == ISD::ABS)
11001 return N0;
11003 if (DAG.SignBitIsZero(N0))
11004 return N0;
11011 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
11012 EVT ExtVT = cast<VTSDNode>(N0.getOperand(1))->getVT();
11019 DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N0.getOperand(0))));
11027 SDValue N0 = N->getOperand(0);
11032 if (SDValue C = DAG.FoldConstantArithmetic(ISD::BSWAP, DL, VT, {N0}))
11035 if (N0.getOpcode() == ISD::BSWAP)
11036 return N0.getOperand(0);
11042 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) {
11043 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0));
11050 if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) {
11051 auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11058 SDValue Res = N0.getOperand(0);
11072 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
11073 N0.hasOneUse()) {
11074 auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11077 SDValue NewSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0));
11078 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL;
11079 return DAG.getNode(InverseShift, DL, VT, NewSwap, N0.getOperand(1));
11090 SDValue N0 = N->getOperand(0);
11095 if (SDValue C = DAG.FoldConstantArithmetic(ISD::BITREVERSE, DL, VT, {N0}))
11099 if (N0.getOpcode() == ISD::BITREVERSE)
11100 return N0.getOperand(0);
11118 SDValue N0 = N->getOperand(0);
11123 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTLZ, DL, VT, {N0}))
11128 if (DAG.isKnownNeverZero(N0))
11129 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, DL, VT, N0);
11135 SDValue N0 = N->getOperand(0);
11141 DAG.FoldConstantArithmetic(ISD::CTLZ_ZERO_UNDEF, DL, VT, {N0}))
11147 SDValue N0 = N->getOperand(0);
11152 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTTZ, DL, VT, {N0}))
11157 if (DAG.isKnownNeverZero(N0))
11158 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, DL, VT, N0);
11164 SDValue N0 = N->getOperand(0);
11170 DAG.FoldConstantArithmetic(ISD::CTTZ_ZERO_UNDEF, DL, VT, {N0}))
11176 SDValue N0 = N->getOperand(0);
11182 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTPOP, DL, VT, {N0}))
11187 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SHL) {
11188 if (ConstantSDNode *AmtC = isConstOrConstSplat(N0.getOperand(1))) {
11191 KnownBits KnownSrc = DAG.computeKnownBits(N0.getOperand(0));
11192 if ((N0.getOpcode() == ISD::SRL &&
11194 (N0.getOpcode() == ISD::SHL &&
11196 return DAG.getNode(ISD::CTPOP, DL, VT, N0.getOperand(0));
11208 TLI.isTruncateFree(N0, HalfVT) && TLI.isZExtFree(HalfVT, VT)) {
11210 if (DAG.MaskedValueIsZero(N0, UpperBits)) {
11212 DAG.getZExtOrTrunc(N0, DL, HalfVT));
11539 SDValue N0 = N->getOperand(0);
11546 if (!sd_match(N0, m_OneUse(m_SetCC(m_Value(Cond0), m_Value(Cond1),
11596 SDValue N0 = N->getOperand(0);
11600 EVT VT0 = N0.getValueType();
11604 if (SDValue V = DAG.simplifySelect(N0, N1, N2))
11611 if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false)) {
11637 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
11638 SDValue Cond0 = N0->getOperand(0);
11639 SDValue Cond1 = N0->getOperand(1);
11650 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
11651 SDValue Cond0 = N0->getOperand(0);
11652 SDValue Cond1 = N0->getOperand(1);
11668 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
11671 SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0);
11676 if (SDValue Combined = visitANDLike(N0, N1_0, N)) {
11687 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
11690 SDValue Or = DAG.getNode(ISD::OR, DL, N0.getValueType(), N0, N2_0);
11695 if (SDValue Combined = visitORLike(N0, N2_0, DL))
11703 if (N0.getOpcode() == ISD::SETCC) {
11704 SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1);
11705 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
11711 if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, N1, N2, Flags, TLI))
11722 CC == ISD::SETUGT && N0.hasOneUse() && isAllOnesConstant(N1) &&
11750 Flags = N0->getFlags();
11752 N2, N0.getOperand(2));
11757 if (SDValue NewSel = SimplifySelect(DL, N0, N1, N2))
11765 if (SDValue R = combineSelectAsExtAnd(N0, N1, N2, DL, DAG))
12274 SDValue N0 = N->getOperand(0);
12279 if (SDValue V = DAG.simplifySelect(N0, N1, N2))
12289 SDValue N0 = N->getOperand(0);
12295 if (SDValue V = DAG.simplifySelect(N0, N1, N2))
12302 if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false))
12308 N0.getScalarValueSizeInBits() == N1.getScalarValueSizeInBits() &&
12309 TLI.getBooleanContents(N0.getValueType()) ==
12313 DAG.getNode(ISD::AND, DL, N0.getValueType(), N1.getOperand(1), N0));
12321 if (N0.getOpcode() == ISD::SETCC) {
12322 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
12323 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
12354 if (N0.hasOneUse() &&
12559 if (ISD::isConstantSplatVectorAllOnes(N0.getNode()))
12562 if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
12570 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
12589 SDValue N0 = N->getOperand(0);
12602 if (CC == ISD::SETEQ && !LegalTypes && N0.getValueType() == MVT::i1 &&
12604 return DAG.getSelect(DL, N2.getValueType(), N0, N3, N2);
12607 if (SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), N0, N1,
12636 return SimplifySelectCC(DL, N0, N1, N2, N3, CC);
12648 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
12651 if (SDValue Combined = SimplifySetCC(VT, N0, N1, Cond, DL, !PreferSetCC)) {
12693 if (IsAndWithShift(N0, N1)) {
12694 AndOrOp = N0;
12696 } else if (IsAndWithShift(N1, N0)) {
12698 ShiftOrRotate = N0;
12699 } else if (IsRotateWithOp(N0, N1)) {
12701 AndOrOp = N0;
12703 } else if (IsRotateWithOp(N1, N0)) {
12706 ShiftOrRotate = N0;
12711 EVT OpVT = N0.getValueType();
12825 SDValue N0 = N->getOperand(0);
12831 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) ||
12832 !N0.hasOneUse())
12835 SDValue Op1 = N0->getOperand(1);
12836 SDValue Op2 = N0->getOperand(2);
12852 (N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes &&
12858 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2);
12871 SDValue N0 = N->getOperand(0);
12880 if (isa<ConstantSDNode>(N0))
12881 return DAG.getNode(Opcode, DL, VT, N0);
12886 if (N0->getOpcode() == ISD::SELECT) {
12887 SDValue Op1 = N0->getOperand(1);
12888 SDValue Op2 = N0->getOperand(2);
12890 (Opcode != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0.getValueType(), VT))) {
12903 return DAG.getSelect(DL, VT, N0->getOperand(0),
12914 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
12919 unsigned EVTBits = N0->getValueType(0).getScalarSizeInBits();
12924 SDValue Op = N0.getOperand(i);
12950 static bool ExtendUsesToFormExtLoad(EVT VT, SDNode *N, SDValue N0,
12955 bool isTruncFree = TLI.isTruncateFree(VT, N0.getValueType());
12956 for (SDNode::use_iterator UI = N0->use_begin(), UE = N0->use_end(); UI != UE;
12961 if (UI.getUse().getResNo() != N0.getResNo())
12972 if (UseOp == N0)
13032 SDValue N0 = N->getOperand(0);
13034 EVT SrcVT = N0.getValueType();
13057 if (N0->getOpcode() != ISD::LOAD)
13060 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
13063 !N0.hasOneUse() || !LN0->isSimple() ||
13069 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI))
13123 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue);
13124 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode());
13125 CombineTo(N0.getNode(), Trunc, NewChain);
13139 SDValue N0 = N->getOperand(0);
13140 if (!ISD::isBitwiseLogicOp(N0.getOpcode()) ||
13141 N0.getOperand(1).getOpcode() != ISD::Constant ||
13142 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT)))
13146 SDValue N1 = N0->getOperand(0);
13164 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND)
13167 if (!N0.hasOneUse() || !N1.hasOneUse())
13184 APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
13185 SDLoc DL0(N0);
13186 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift,
13199 // N0 is dead at this point.
13200 recursivelyDeleteUnusedNodes(N0.getNode());
13255 SDValue N0, ISD::LoadExtType ExtLoadType) {
13256 SDNode *N0Node = N0.getNode();
13260 !ISD::isUNINDEXEDLoad(N0Node) || !N0.hasOneUse())
13263 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
13286 bool LegalOperations, SDNode *N, SDValue N0,
13290 if (!ISD::isNON_EXTLoad(N0.getNode()) || !ISD::isUNINDEXEDLoad(N0.getNode()))
13297 for (SDNode *User : N0->uses()) {
13313 !cast<LoadSDNode>(N0)->isSimple()) &&
13314 !TLI.isLoadExtLegal(ExtLoadType, VT, N0.getValueType()))
13319 if (!N0.hasOneUse())
13320 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI);
13326 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
13328 LN0->getBasePtr(), N0.getValueType(),
13330 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc);
13339 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad);
13347 bool LegalOperations, SDNode *N, SDValue N0,
13349 if (!N0.hasOneUse())
13352 MaskedLoadSDNode *Ld = dyn_cast<MaskedLoadSDNode>(N0);
13356 if ((LegalOperations || !cast<MaskedLoadSDNode>(N0)->isSimple()) &&
13376 SDValue N0,
13378 auto *ALoad = dyn_cast<AtomicSDNode>(N0);
13441 SDValue N0 = N->getOperand(0);
13442 if (N0.getOpcode() != ISD::SETCC)
13445 SDValue N00 = N0.getOperand(0);
13446 SDValue N01 = N0.getOperand(1);
13447 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
13453 SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags());
13464 if (SVT != N0.getValueType()) {
13484 if (N0.hasOneUse() && TLI.isOperationLegalOrCustom(ISD::SETCC, VT) &&
13511 if (UI.getUse().getResNo() != 0 || User == N0.getNode())
13533 unsigned SetCCWidth = N0.getScalarValueSizeInBits();
13549 if (!VT.isVector() && !shouldConvertSelectOfConstantsToMath(N0, VT, TLI)) {
13566 SDValue N0 = N->getOperand(0);
13575 if (N0.isUndef())
13583 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
13584 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0));
13588 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
13589 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)
13591 N0.getOperand(0));
13594 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
13595 SDValue N00 = N0.getOperand(0);
13596 EVT ExtVT = cast<VTSDNode>(N0->getOperand(1))->getVT();
13604 if (N0.getOpcode() == ISD::TRUNCATE) {
13607 if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) {
13608 SDNode *oye = N0.getOperand(0).getNode();
13609 if (NarrowLoad.getNode() != N0.getNode()) {
13610 CombineTo(N0.getNode(), NarrowLoad);
13619 SDValue Op = N0.getOperand(0);
13621 unsigned MidBits = N0.getScalarValueSizeInBits();
13644 N0.getValueType())) {
13646 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
13648 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
13650 DAG.getValueType(N0.getValueType()));
13656 tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0,
13661 tryToFoldExtOfMaskedLoad(DAG, TLI, VT, LegalOperations, N, N0,
13672 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::SEXTLOAD))
13677 tryToFoldExtOfAtomicLoad(DAG, TLI, VT, N0, ISD::SEXTLOAD))
13682 if (ISD::isBitwiseLogicOp(N0.getOpcode()) &&
13683 isa<LoadSDNode>(N0.getOperand(0)) &&
13684 N0.getOperand(1).getOpcode() == ISD::Constant &&
13685 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
13686 LoadSDNode *LN00 = cast<LoadSDNode>(N0.getOperand(0));
13691 bool DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0),
13698 APInt Mask = N0.getConstantOperandAPInt(1).sext(VT.getSizeInBits());
13699 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
13701 ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::SIGN_EXTEND);
13702 bool NoReplaceTruncAnd = !N0.hasOneUse();
13705 // If N0 has multiple uses, change other uses as well.
13708 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And);
13709 CombineTo(N0.getNode(), TruncAnd);
13730 if (!TLI.isSExtCheaperThanZExt(N0.getValueType(), VT) &&
13732 DAG.SignBitIsZero(N0)) {
13735 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0, Flags);
13743 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
13744 isNullOrNullSplat(N0.getOperand(0)) &&
13745 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND &&
13747 SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(1).getOperand(0), DL, VT);
13752 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
13753 isAllOnesOrAllOnesSplat(N0.getOperand(1)) &&
13754 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
13756 SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT);
13762 if (N0.getValueType() == MVT::i1 && isBitwiseNot(N0) && N0.hasOneUse() &&
13766 if (SDValue NewXor = visitXOR(N0.getNode())) {
13767 // Returning N0 is a form of in-visit replacement that may have
13768 // invalidated N0.
13769 if (NewXor.getNode() == N0.getNode()) {
13779 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
13840 SDValue N0 = N->getOperand(0);
13849 if (N0.isUndef())
13857 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
13859 if (N0.getOpcode() == ISD::ZERO_EXTEND)
13860 Flags.setNonNeg(N0->getFlags().hasNonNeg());
13861 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0), Flags);
13866 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
13867 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG)
13868 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, N0.getOperand(0));
13875 if (isTruncateOf(DAG, N0, Op, Known)) {
13877 (Op.getScalarValueSizeInBits() == N0.getScalarValueSizeInBits()) ?
13880 N0.getScalarValueSizeInBits(),
13885 DAG.salvageDebugInfo(*N0.getNode());
13892 if (N0.getOpcode() == ISD::TRUNCATE) {
13895 if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) {
13896 SDNode *oye = N0.getOperand(0).getNode();
13897 if (NarrowLoad.getNode() != N0.getNode()) {
13898 CombineTo(N0.getNode(), NarrowLoad);
13905 EVT SrcVT = N0.getOperand(0).getValueType();
13906 EVT MinVT = N0.getValueType();
13909 SDValue Op = N0.getOperand(0);
13939 SDValue Op = N0.getOperand(0);
13943 // Transfer the debug info; the new node is equivalent to N0.
13944 DAG.transferDbgValues(N0, ZExtOrTrunc);
13950 SDValue Op = DAG.getAnyExtOrTrunc(N0.getOperand(0), DL, VT);
13955 DAG.transferDbgValues(N0, And);
13962 if (N0.getOpcode() == ISD::AND &&
13963 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
13964 N0.getOperand(1).getOpcode() == ISD::Constant &&
13965 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0), N0.getValueType()) ||
13966 !TLI.isZExtFree(N0.getValueType(), VT))) {
13967 SDValue X = N0.getOperand(0).getOperand(0);
13969 APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
13976 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD,
13981 tryToFoldExtOfMaskedLoad(DAG, TLI, VT, LegalOperations, N, N0,
13992 tryToFoldExtOfAtomicLoad(DAG, TLI, VT, N0, ISD::ZEXTLOAD))
13999 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && !TLI.isZExtFree(N0, VT) &&
14000 isa<LoadSDNode>(N0.getOperand(0)) &&
14001 N0.getOperand(1).getOpcode() == ISD::Constant &&
14002 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
14003 LoadSDNode *LN00 = cast<LoadSDNode>(N0.getOperand(0));
14009 if (!N0.hasOneUse()) {
14010 if (N0.getOpcode() == ISD::AND) {
14011 auto *AndC = cast<ConstantSDNode>(N0.getOperand(1));
14019 DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0),
14026 APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
14027 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
14029 ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::ZERO_EXTEND);
14030 bool NoReplaceTruncAnd = !N0.hasOneUse();
14033 // If N0 has multiple uses, change other uses as well.
14036 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And);
14037 CombineTo(N0.getNode(), TruncAnd);
14058 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD))
14064 if (N0.getOpcode() == ISD::SETCC) {
14066 SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags());
14070 N0.getValueType().getVectorElementType() == MVT::i1) {
14071 EVT N00VT = N0.getOperand(0).getValueType();
14072 if (getSetCCResultType(N00VT) == N0.getValueType())
14082 SDValue VSetCC = DAG.getNode(ISD::SETCC, DL, VT, N0.getOperand(0),
14083 N0.getOperand(1), N0.getOperand(2));
14084 return DAG.getZeroExtendInReg(VSetCC, DL, N0.getValueType());
14092 DAG.getNode(ISD::SETCC, DL, MatchingVectorType, N0.getOperand(0),
14093 N0.getOperand(1), N0.getOperand(2));
14095 N0.getValueType());
14099 EVT N0VT = N0.getValueType();
14100 EVT N00VT = N0.getOperand(0).getValueType();
14102 DL, N0.getOperand(0), N0.getOperand(1),
14105 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
14110 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
14111 !TLI.isZExtFree(N0, VT)) {
14112 SDValue ShVal = N0.getOperand(0);
14113 SDValue ShAmt = N0.getOperand(1);
14115 if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) {
14116 if (N0.getOpcode() == ISD::SHL) {
14139 return DAG.getNode(N0.getOpcode(), DL, VT,
14158 if (N->getFlags().hasNonNeg() && !TLI.isZExtFree(N0.getValueType(), VT)) {
14159 SDNode *CSENode = DAG.getNodeIfExists(ISD::SIGN_EXTEND, N->getVTList(), N0);
14168 SDValue N0 = N->getOperand(0);
14173 if (N0.isUndef())
14182 if (N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::ZERO_EXTEND ||
14183 N0.getOpcode() == ISD::SIGN_EXTEND) {
14185 if (N0.getOpcode() == ISD::ZERO_EXTEND)
14186 Flags.setNonNeg(N0->getFlags().hasNonNeg());
14187 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Flags);
14193 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
14194 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG ||
14195 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)
14196 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
14200 if (N0.getOpcode() == ISD::TRUNCATE) {
14201 if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) {
14202 SDNode *oye = N0.getOperand(0).getNode();
14203 if (NarrowLoad.getNode() != N0.getNode()) {
14204 CombineTo(N0.getNode(), NarrowLoad);
14213 if (N0.getOpcode() == ISD::TRUNCATE)
14214 return DAG.getAnyExtOrTrunc(N0.getOperand(0), DL, VT);
14218 if (N0.getOpcode() == ISD::AND &&
14219 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
14220 N0.getOperand(1).getOpcode() == ISD::Constant &&
14221 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0), N0.getValueType())) {
14222 SDValue X = DAG.getAnyExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT);
14223 SDValue Y = DAG.getNode(ISD::ANY_EXTEND, DL, VT, N0.getOperand(1));
14234 tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0,
14237 } else if (ISD::isNON_EXTLoad(N0.getNode()) &&
14238 ISD::isUNINDEXEDLoad(N0.getNode()) &&
14239 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
14242 if (!N0.hasOneUse())
14244 ExtendUsesToFormExtLoad(VT, N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
14246 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14248 LN0->getBasePtr(), N0.getValueType(),
14250 ExtendSetCCUses(SetCCs, N0, ExtLoad, ISD::ANY_EXTEND);
14252 bool NoReplaceTrunc = N0.hasOneUse();
14259 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad);
14269 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) &&
14270 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
14271 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14285 if (N0.getOpcode() == ISD::SETCC) {
14287 SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags());
14295 EVT N00VT = N0.getOperand(0).getValueType();
14296 if (getSetCCResultType(N00VT) == N0.getValueType())
14305 return DAG.getSetCC(DL, VT, N0.getOperand(0), N0.getOperand(1),
14306 cast<CondCodeSDNode>(N0.getOperand(2))->get());
14313 DL, MatchingVectorType, N0.getOperand(0), N0.getOperand(1),
14314 cast<CondCodeSDNode>(N0.getOperand(2))->get());
14320 DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT),
14322 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
14337 SDValue N0 = N->getOperand(0);
14342 if (N0.getOpcode() == Opcode &&
14343 AssertVT == cast<VTSDNode>(N0.getOperand(1))->getVT())
14344 return N0;
14346 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
14347 N0.getOperand(0).getOpcode() == Opcode) {
14354 SDValue BigA = N0.getOperand(0);
14366 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
14367 N0.getOperand(0).getOpcode() == ISD::AssertSext &&
14369 SDValue BigA = N0.getOperand(0);
14386 SDValue N0 = N->getOperand(0);
14390 if (auto *AAN = dyn_cast<AssertAlignSDNode>(N0))
14391 return DAG.getAssertAlign(DL, N0.getOperand(0),
14397 switch (N0.getOpcode()) {
14403 SDValue LHS = N0.getOperand(0);
14404 SDValue RHS = N0.getOperand(1);
14412 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS);
14428 SDValue N0 = N->getOperand(0);
14457 auto *LN = dyn_cast<LoadSDNode>(N0);
14503 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) {
14504 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0;
14577 N0 = SRL.getOperand(0);
14586 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
14587 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
14588 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
14590 N0 = N0.getOperand(0);
14595 if (!isa<LoadSDNode>(N0))
14598 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14640 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
14671 SDValue N0 = N->getOperand(0);
14679 if (N0.isUndef())
14683 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
14684 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
14687 if (ExtVTBits >= DAG.ComputeMaxSignificantBits(N0))
14688 return N0;
14691 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
14692 ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
14693 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0.getOperand(0),
14700 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
14701 SDValue N00 = N0.getOperand(0);
14712 if (ISD::isExtVecInRegOpcode(N0.getOpcode())) {
14713 SDValue N00 = N0.getOperand(0);
14715 unsigned DstElts = N0.getValueType().getVectorMinNumElements();
14717 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
14729 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
14730 SDValue N00 = N0.getOperand(0);
14737 if (DAG.MaskedValueIsZero(N0, APInt::getOneBitSet(VTBits, ExtVTBits - 1)))
14738 return DAG.getZeroExtendInReg(N0, SDLoc(N), ExtVT);
14753 if (N0.getOpcode() == ISD::SRL) {
14754 if (auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
14758 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
14760 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
14761 N0.getOperand(1));
14769 if (ISD::isEXTLoad(N0.getNode()) &&
14770 ISD::isUNINDEXEDLoad(N0.getNode()) &&
14771 ExtVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
14772 ((!LegalOperations && cast<LoadSDNode>(N0)->isSimple() &&
14773 N0.hasOneUse()) ||
14775 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14781 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
14787 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
14788 N0.hasOneUse() &&
14789 ExtVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
14790 ((!LegalOperations && cast<LoadSDNode>(N0)->isSimple()) &&
14792 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14798 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
14804 if (MaskedLoadSDNode *Ld = dyn_cast<MaskedLoadSDNode>(N0)) {
14805 if (ExtVT == Ld->getMemoryVT() && N0.hasOneUse() &&
14813 CombineTo(N0.getNode(), ExtMaskedLoad, ExtMaskedLoad.getValue(1));
14819 if (auto *GN0 = dyn_cast<MaskedGatherSDNode>(N0)) {
14831 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
14838 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) {
14839 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
14840 N0.getOperand(1), false))
14848 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() &&
14849 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) {
14850 SDValue InnerExt = N0.getOperand(0);
14860 N0.getOperand(1));
14900 SDValue N0 = N->getOperand(0);
14904 if (N0.isUndef()) {
14926 SDValue N0 = N->getOperand(0);
14928 EVT SrcVT = N0.getValueType();
14933 if (N0.isUndef())
14937 if (N0.getOpcode() == ISD::TRUNCATE)
14938 return DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
14941 if (SDValue C = DAG.FoldConstantArithmetic(ISD::TRUNCATE, DL, VT, {N0}))
14945 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
14946 N0.getOpcode() == ISD::SIGN_EXTEND ||
14947 N0.getOpcode() == ISD::ANY_EXTEND) {
14949 if (N0.getOperand(0).getValueType().bitsLT(VT))
14950 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
14952 if (N0.getOperand(0).getValueType().bitsGT(VT))
14953 return DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
14956 return N0.getOperand(0);
14961 if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
14962 N0.hasOneUse()) {
14963 SDValue X = N0.getOperand(0);
14964 SDValue ExtVal = N0.getOperand(1);
14986 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
14987 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
14988 EVT VecTy = N0.getOperand(0).getValueType();
14989 EVT ExTy = N0.getValueType();
14999 SDValue EltNo = N0->getOperand(1);
15004 DAG.getBitcast(NVT, N0.getOperand(0)),
15010 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse()) {
15013 SDLoc SL(N0);
15014 SDValue Cond = N0.getOperand(0);
15015 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
15016 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
15022 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
15025 SDValue Amt = N0.getOperand(1);
15030 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15039 if (SDValue V = foldSubToUSubSat(VT, N0.getNode(), DL))
15046 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
15047 N0.hasOneUse() &&
15053 for (const SDValue &Op : N0->op_values()) {
15061 if (N0.getOpcode() == ISD::SPLAT_VECTOR &&
15066 VT, DL, DAG.getNode(ISD::TRUNCATE, DL, SVT, N0->getOperand(0)));
15074 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
15075 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
15076 N0.getOperand(0).hasOneUse()) {
15077 SDValue BuildVect = N0.getOperand(0);
15101 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
15107 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
15108 auto *LN0 = cast<LoadSDNode>(N0);
15113 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
15121 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
15127 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
15128 SDValue X = N0.getOperand(i);
15166 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
15167 SDValue VecSrc = N0.getOperand(0);
15186 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
15187 SDValue N00 = N0.getOperand(0);
15193 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT,
15194 N00.getOperand(0), N0.getOperand(1));
15205 switch (N0.getOpcode()) {
15212 if (!LegalOperations && N0.hasOneUse() &&
15213 (isConstantOrConstantVector(N0.getOperand(0), true) ||
15214 isConstantOrConstantVector(N0.getOperand(1), true))) {
15218 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) {
15219 SDValue NarrowL = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15220 SDValue NarrowR = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1));
15221 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR);
15232 if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) ||
15233 TLI.isOperationLegal(N0.getOpcode(), VT)) &&
15234 N0.hasOneUse() && !N0->hasAnyUseOfValue(1)) {
15235 SDValue X = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15236 SDValue Y = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1));
15237 SDVTList VTs = DAG.getVTList(VT, N0->getValueType(1));
15238 return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2));
15245 if (!LegalOperations && N0.hasOneUse() &&
15246 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
15247 N0.getOperand(0).getOperand(0).getScalarValueSizeInBits() <=
15249 hasOperation(N0.getOpcode(), VT)) {
15250 return getTruncatedUSUBSAT(VT, SrcVT, N0.getOperand(0), N0.getOperand(1),
15309 SDValue N0 = N->getOperand(0);
15310 EVT SourceVT = N0.getValueType();
15322 switch (N0.getOpcode()) {
15356 SDValue LogicOp0 = N0.getOperand(0);
15357 ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true);
15363 if (N0.getOpcode() == ISD::OR)
15372 SDValue N0 = N->getOperand(0);
15375 if (N0.isUndef())
15386 (!LegalOperations && VT.isInteger() && N0.getValueType().isInteger() &&
15388 N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() &&
15389 cast<BuildVectorSDNode>(N0)->isConstant())
15390 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(),
15394 if (isIntOrFPConstant(N0)) {
15399 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
15401 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() &&
15403 SDValue C = DAG.getBitcast(VT, N0);
15410 if (N0.getOpcode() == ISD::BITCAST)
15411 return DAG.getBitcast(VT, N0.getOperand(0));
15415 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && VT.isInteger() &&
15416 !TLI.isTypeLegal(N0.getOperand(0).getValueType())) {
15423 if (IsFreeBitcast(N0.getOperand(0)) && IsFreeBitcast(N0.getOperand(1)))
15424 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
15425 DAG.getBitcast(VT, N0.getOperand(0)),
15426 DAG.getBitcast(VT, N0.getOperand(1)));
15431 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
15433 TLI.hasBigEndianPartOrdering(N0.getValueType(), DAG.getDataLayout()) ==
15440 ((!LegalOperations && cast<LoadSDNode>(N0)->isSimple()) ||
15442 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
15444 if (TLI.isLoadBitCastBeneficial(N0.getValueType(), VT, DAG,
15449 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
15469 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
15470 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
15471 N0->hasOneUse() && VT.isInteger() && !VT.isVector() &&
15472 !N0.getValueType().isVector()) {
15473 SDValue NewConv = DAG.getBitcast(VT, N0.getOperand(0));
15477 if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
15480 APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64);
15482 if (N0.getOpcode() == ISD::FNEG) {
15486 assert(N0.getOpcode() == ISD::FABS);
15492 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit);
15496 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);
15501 if (N0.getOpcode() == ISD::FNEG)
15504 assert(N0.getOpcode() == ISD::FABS);
15520 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() &&
15521 isa<ConstantFPSDNode>(N0.getOperand(0)) && VT.isInteger() &&
15523 unsigned OrigXWidth = N0.getOperand(1).getValueSizeInBits();
15526 SDValue X = DAG.getBitcast(IntXVT, N0.getOperand(1));
15547 if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
15549 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));
15551 SDValue X = DAG.getBitcast(VT, N0.getOperand(1));
15553 SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X);
15565 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);
15574 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));
15584 if (N0.getOpcode() == ISD::BUILD_PAIR)
15585 if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT))
15593 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() &&
15594 VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() &&
15595 !(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) {
15596 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N0);
15612 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
15613 SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
15618 VT.getVectorNumElements() / N0.getValueType().getVectorNumElements();
15639 SDValue N0 = N->getOperand(0);
15641 if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false))
15642 return N0;
15647 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
15657 if (DAG.canCreateUndefOrPoison(N0, /*PoisonOnly*/ false,
15659 N0->getNumValues() != 1 || !N0->hasOneUse())
15663 N0.getOpcode() == ISD::SELECT_CC ||
15664 N0.getOpcode() == ISD::SETCC ||
15665 N0.getOpcode() == ISD::BUILD_VECTOR ||
15666 N0.getOpcode() == ISD::BUILD_PAIR ||
15667 N0.getOpcode() == ISD::VECTOR_SHUFFLE ||
15668 N0.getOpcode() == ISD::CONCAT_VECTORS;
15676 if (N0.getOpcode() == ISD::BUILD_VECTOR) {
15677 SDLoc DL(N0);
15678 EVT VT = N0.getValueType();
15679 if (llvm::ISD::isBuildVectorAllOnes(N0.getNode()))
15681 if (llvm::ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
15683 for (const SDValue &Op : N0->op_values())
15692 for (auto [OpNo, Op] : enumerate(N0->ops())) {
15712 // N0 can mutate during iteration, so make sure to refetch the maybe poison
15745 N0 = N->getOperand(0);
15749 SmallVector<SDValue> Ops(N0->op_begin(), N0->op_end());
15757 if (auto *SVN = dyn_cast<ShuffleVectorSDNode>(N0)) {
15759 R = DAG.getVectorShuffle(N0.getValueType(), SDLoc(N0), Ops[0], Ops[1],
15763 R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops);
15864 SDValue N0 = N->getOperand(0);
15897 if (N0 == N1)
15920 if (Aggressive && isContractableFMUL(N0) && isContractableFMUL(N1)) {
15921 if (N0->use_size() > N1->use_size())
15922 std::swap(N0, N1);
15926 if (isContractableFMUL(N0) && (Aggressive || N0->hasOneUse())) {
15927 return matcher.getNode(PreferredFusedOpcode, SL, VT, N0.getOperand(0),
15928 N0.getOperand(1), N1);
15935 N1.getOperand(1), N0);
15950 if (isFusedOp(N0) && N0.hasOneUse()) {
15951 FMA = N0;
15955 E = N0;
15978 if (matcher.match(N0, ISD::FP_EXTEND)) {
15979 SDValue N00 = N0.getOperand(0);
16000 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0);
16016 if (isFusedOp(N0)) {
16017 SDValue N02 = N0.getOperand(2);
16023 return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1),
16045 if (N0.getOpcode() == ISD::FP_EXTEND) {
16046 SDValue N00 = N0.getOperand(0);
16070 N0);
16089 N0);
16101 SDValue N0 = N->getOperand(0);
16172 if (isContractableFMUL(N0) && isContractableFMUL(N1) &&
16173 (N0->use_size() > N1->use_size())) {
16175 if (SDValue V = tryToFoldXSubYZ(N0, N1))
16178 if (SDValue V = tryToFoldXYSubZ(N0, N1))
16182 if (SDValue V = tryToFoldXYSubZ(N0, N1))
16185 if (SDValue V = tryToFoldXSubYZ(N0, N1))
16190 if (matcher.match(N0, ISD::FNEG) && isContractableFMUL(N0.getOperand(0)) &&
16191 (Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) {
16192 SDValue N00 = N0.getOperand(0).getOperand(0);
16193 SDValue N01 = N0.getOperand(0).getOperand(1);
16203 if (matcher.match(N0, ISD::FP_EXTEND)) {
16204 SDValue N00 = N0.getOperand(0);
16229 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0);
16239 if (matcher.match(N0, ISD::FP_EXTEND)) {
16240 SDValue N00 = N0.getOperand(0);
16263 if (matcher.match(N0, ISD::FNEG)) {
16264 SDValue N00 = N0.getOperand(0);
16299 if (CanFuse && isFusedOp(N0) &&
16300 isContractableAndReassociableFMUL(N0.getOperand(2)) &&
16301 N0->hasOneUse() && N0.getOperand(2)->hasOneUse()) {
16303 PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1),
16305 N0.getOperand(2).getOperand(0),
16306 N0.getOperand(2).getOperand(1),
16322 matcher.getNode(ISD::FNEG, SL, VT, N20), N21, N0));
16327 if (isFusedOp(N0) && N0->hasOneUse()) {
16328 SDValue N02 = N0.getOperand(2);
16335 PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1),
16351 if (matcher.match(N0, ISD::FP_EXTEND)) {
16352 SDValue N00 = N0.getOperand(0);
16389 matcher.getNode(ISD::FP_EXTEND, SL, VT, N1201), N0));
16418 matcher.getNode(ISD::FP_EXTEND, SL, VT, N1021), N0));
16430 SDValue N0 = N->getOperand(0);
16441 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1;
16480 if (SDValue FMA = FuseFADD(N0, N1))
16482 if (SDValue FMA = FuseFADD(N1, N0))
16513 if (SDValue FMA = FuseFSUB(N0, N1))
16515 if (SDValue FMA = FuseFSUB(N1, N0))
16534 SDValue N0 = N->getOperand(0);
16536 SDNode *N0CFP = DAG.isConstantFPBuildVectorOrConstantFP(N0);
16544 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
16548 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FADD, DL, VT, {N0, N1}))
16553 return DAG.getNode(ISD::FADD, DL, VT, N1, N0);
16560 // N0 + -0.0 --> N0 (also allowed with +0.0 and fast-math)
16564 return N0;
16573 return DAG.getNode(ISD::FSUB, DL, VT, N0, NegN1);
16578 N0, DAG, LegalOperations, ForCodeSize))
16589 if (isFMulNegTwo(N0)) {
16590 SDValue B = N0.getOperand(0);
16598 return DAG.getNode(ISD::FSUB, DL, VT, N0, Add);
16608 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
16612 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
16623 if (N1CFP && N0.getOpcode() == ISD::FADD &&
16624 DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) {
16625 SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1);
16626 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC);
16633 if (N0.getOpcode() == ISD::FMUL) {
16635 DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0));
16637 DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1));
16640 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
16641 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
16649 N0.getOperand(0) == N1.getOperand(0)) {
16650 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
16652 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP);
16663 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
16666 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP);
16670 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
16671 N0.getOperand(0) == N0.getOperand(1) &&
16672 N1.getOperand(0) == N0.getOperand(0)) {
16679 if (N0.getOpcode() == ISD::FADD) {
16681 DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0));
16683 if (!CFP00 && N0.getOperand(0) == N0.getOperand(1) &&
16684 (N0.getOperand(0) == N1)) {
16695 N1.getOperand(0) == N0) {
16696 return DAG.getNode(ISD::FMUL, DL, VT, N0,
16702 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
16703 N0.getOperand(0) == N0.getOperand(1) &&
16705 N0.getOperand(0) == N1.getOperand(0)) {
16706 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0),
16713 VT, N0, N1, Flags))
16728 SDValue N0 = N->getOperand(1);
16740 {Chain, N0, NegN1});
16746 N0, DAG, LegalOperations, ForCodeSize)) {
16754 SDValue N0 = N->getOperand(0);
16756 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true);
16764 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
16768 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FSUB, DL, VT, {N0, N1}))
16783 return N0;
16787 if (N0 == N1) {
16816 if (N0 == N1->getOperand(0))
16819 if (N0 == N1->getOperand(1))
16826 return DAG.getNode(ISD::FADD, DL, VT, N0, NegN1);
16944 SDValue N0 = N->getOperand(0);
16953 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
16957 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FMUL, DL, VT, {N0, N1}))
16961 if (DAG.isConstantFPBuildVectorOrConstantFP(N0) &&
16963 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0);
16976 N0.getOpcode() == ISD::FMUL) {
16977 SDValue N00 = N0.getOperand(0);
16978 SDValue N01 = N0.getOperand(1);
16990 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() &&
16991 N0.getOperand(0) == N0.getOperand(1)) {
16994 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts);
16999 VT, N0, N1, Flags))
17005 return DAG.getNode(ISD::FADD, DL, VT, N0, N0);
17011 DAG.getConstantFP(-0.0, DL, VT), N0, Flags);
17015 // -N0 * -N1 --> N0 * N1
17021 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0);
17034 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
17036 SDValue Select = N0, X = N1;
17092 SDValue N0 = N->getOperand(0);
17095 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
17105 if (isa<ConstantFPSDNode>(N0) &&
17108 return matcher.getNode(ISD::FMA, DL, VT, N0, N1, N2);
17111 // (-N0 * -N1) + N2 --> (N0 * N1) + N2
17117 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0);
17139 return matcher.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
17142 if (DAG.isConstantFPBuildVectorOrConstantFP(N0) &&
17144 return matcher.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
17150 if (matcher.match(N2, ISD::FMUL) && N0 == N2.getOperand(0) &&
17154 ISD::FMUL, DL, VT, N0,
17159 if (matcher.match(N0, ISD::FMUL) &&
17161 DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) {
17163 ISD::FMA, DL, VT, N0.getOperand(0),
17164 matcher.getNode(ISD::FMUL, DL, VT, N1, N0.getOperand(1)), N2);
17172 return matcher.getNode(ISD::FADD, DL, VT, N0, N2);
17176 SDValue RHSNeg = matcher.getNode(ISD::FNEG, DL, VT, N0);
17182 if (matcher.match(N0, ISD::FNEG) &&
17186 return matcher.getNode(ISD::FMA, DL, VT, N0.getOperand(0),
17194 if (N1CFP && N0 == N2) {
17195 return matcher.getNode(ISD::FMUL, DL, VT, N0,
17201 if (N1CFP && matcher.match(N2, ISD::FNEG) && N2.getOperand(0) == N0) {
17202 return matcher.getNode(ISD::FMUL, DL, VT, N0,
17218 SDValue N0 = N->getOperand(0);
17225 if (isa<ConstantFPSDNode>(N0) && isa<ConstantFPSDNode>(N1) &&
17227 return DAG.getNode(ISD::FMAD, DL, VT, N0, N1, N2);
17249 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
17250 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, /* AllowUndefs */ true);
17313 SDValue N0 = N->getOperand(0);
17321 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17325 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FDIV, DL, VT, {N0, N1}))
17357 return DAG.getNode(ISD::FMUL, DL, VT, N0,
17366 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
17373 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
17381 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
17411 return DAG.getNode(ISD::FMUL, DL, VT, N0, Rsqrt);
17423 return DAG.getNode(ISD::FMUL, DL, VT, N0, Div);
17430 if (SDValue RV = BuildDivEstimate(N0, N1, Flags))
17437 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0))
17446 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0);
17463 SDValue N0 = N->getOperand(0);
17470 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17474 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, DL, VT, {N0, N1}))
17480 // Lower frem N0, N1 => x - trunc(N0 / N1) * N1, providing N1 is an integer
17488 !Flags.hasNoSignedZeros() && !DAG.cannotBeOrderedNegativeFP(N0);
17489 SDValue Div = DAG.getNode(ISD::FDIV, DL, VT, N0, N1);
17494 N1, N0);
17497 MLA = DAG.getNode(ISD::FSUB, DL, VT, N0, Mul);
17499 return NeedsCopySign ? DAG.getNode(ISD::FCOPYSIGN, DL, VT, MLA, N0) : MLA;
17515 SDValue N0 = N->getOperand(0);
17516 if (TLI.isFsqrtCheap(N0, DAG))
17520 // TODO: If this is N0/sqrt(N0), and we reach this node before trying to
17524 return buildSqrtEstimate(N0, Flags);
17556 SDValue N0 = N->getOperand(0);
17562 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FCOPYSIGN, DL, VT, {N0, N1}))
17571 return DAG.getNode(ISD::FABS, DL, VT, N0);
17575 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
17582 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
17583 N0.getOpcode() == ISD::FCOPYSIGN)
17584 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0.getOperand(0), N1);
17588 return DAG.getNode(ISD::FABS, DL, VT, N0);
17592 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0, N1.getOperand(1));
17597 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0, N1.getOperand(0));
17606 if (SimplifyDemandedBits(N0,
17705 SDValue N0 = N->getOperand(0);
17706 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT &&
17707 N0.getOperand(0).getValueType() == VT)
17708 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));
17710 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT &&
17711 N0.getOperand(0).getValueType() == VT)
17712 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0.getOperand(0));
17718 SDValue N0 = N->getOperand(0);
17720 EVT OpVT = N0.getValueType();
17723 if (N0.isUndef())
17727 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
17731 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
17738 if (DAG.SignBitIsZero(N0))
17739 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
17744 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
17748 return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(-1.0, DL, VT),
17754 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
17755 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() &&
17758 return DAG.getSelect(DL, VT, N0.getOperand(0),
17770 SDValue N0 = N->getOperand(0);
17772 EVT OpVT = N0.getValueType();
17775 if (N0.isUndef())
17779 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
17783 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
17790 if (DAG.SignBitIsZero(N0))
17791 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
17795 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
17798 return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(1.0, DL, VT),
17810 SDValue N0 = N->getOperand(0);
17813 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
17816 SDValue Src = N0.getOperand(0);
17818 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
17833 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType());
17851 SDValue N0 = N->getOperand(0);
17855 if (N0.isUndef())
17859 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
17860 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
17866 SDValue N0 = N->getOperand(0);
17870 if (N0.isUndef())
17874 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
17875 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
17881 SDValue N0 = N->getOperand(0);
17885 if (N0.isUndef())
17889 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
17890 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N0);
17896 SDValue N0 = N->getOperand(0);
17902 DAG.FoldConstantArithmetic(ISD::FP_ROUND, SDLoc(N), VT, {N0, N1}))
17906 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
17907 return N0.getOperand(0);
17910 if (N0.getOpcode() == ISD::FP_ROUND) {
17912 const bool N0IsTrunc = N0.getConstantOperandVal(1) == 1;
17925 if (N0.getOperand(0).getValueType() == MVT::f80 && VT == MVT::f16)
17936 ISD::FP_ROUND, DL, VT, N0.getOperand(0),
17946 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() &&
17948 N0.getValueType())) {
17949 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
17950 N0.getOperand(0), N1);
17953 Tmp, N0.getOperand(1));
17963 SDValue N0 = N->getOperand(0);
17976 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
17977 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
17980 if (N0.getOpcode() == ISD::FP16_TO_FP &&
17982 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0));
17986 if (N0.getOpcode() == ISD::FP_ROUND
17987 && N0.getConstantOperandVal(1) == 1) {
17988 SDValue In = N0.getOperand(0);
17992 In, N0.getOperand(1));
17997 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
17998 TLI.isLoadExtLegalOrCustom(ISD::EXTLOAD, VT, N0.getValueType())) {
17999 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
18002 LN0->getBasePtr(), N0.getValueType(),
18006 N0.getNode(),
18007 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), N0.getValueType(), ExtLoad,
18008 DAG.getIntPtrConstant(1, SDLoc(N0), /*isTarget=*/true)),
18020 SDValue N0 = N->getOperand(0);
18024 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
18025 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
18031 SDValue N0 = N->getOperand(0);
18035 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
18036 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
18041 switch (N0.getOpcode()) {
18049 return N0;
18056 SDValue N0 = N->getOperand(0);
18059 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
18060 return DAG.getNode(ISD::FFREXP, SDLoc(N), N->getVTList(), N0);
18065 SDValue N0 = N->getOperand(0);
18069 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
18070 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
18076 SDValue N0 = N->getOperand(0);
18081 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
18082 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
18085 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize))
18092 if (N0.getOpcode() == ISD::FSUB &&
18094 N->getFlags().hasNoSignedZeros()) && N0.hasOneUse()) {
18095 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0.getOperand(1),
18096 N0.getOperand(0));
18106 SDValue N0 = N->getOperand(0);
18116 if (SDValue C = DAG.FoldConstantArithmetic(Opc, SDLoc(N), VT, {N0, N1}))
18120 if (DAG.isConstantFPBuildVectorOrConstantFP(N0) &&
18122 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
18157 Opc, SDLoc(N), VT, N0, N1, Flags))
18164 SDValue N0 = N->getOperand(0);
18168 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
18169 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
18172 if (N0.getOpcode() == ISD::FABS)
18177 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
18178 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
19927 SDValue N0 = Value.getOperand(0);
19928 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
19929 Chain == SDValue(N0.getNode(), 1)) {
19930 LoadSDNode *LD = cast<LoadSDNode>(N0);
19987 DAG.getLoad(NewVT, SDLoc(N0), LD->getChain(), NewPtr,
20001 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
24623 SDValue N0 = N->getOperand(0);
24627 EVT WideVT = N0.getValueType();
24632 auto *WideShuffleVector = dyn_cast<ShuffleVectorSDNode>(N0);
24977 SDValue N0 = Shuf->getOperand(0), N1 = Shuf->getOperand(1);
24978 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
24980 !N0.getOperand(1).isUndef() || !N1.getOperand(1).isUndef())
25014 SDValue X = N0.getOperand(0), Y = N1.getOperand(0);
25027 SDValue N0 = N->getOperand(0);
25033 EVT ConcatVT = N0.getOperand(0).getValueType();
25045 N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0),
25046 N0.getOperand(1),
25049 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1);
25077 if (OpIdx < (int)N0.getNumOperands())
25078 Ops.push_back(N0.getOperand(OpIdx));
25080 Ops.push_back(N1.getOperand(OpIdx - N0.getNumOperands()));
25107 SDValue N0 = SVN->getOperand(0);
25110 if (!N0->hasOneUse())
25119 bool N0AnyConst = isAnyConstantBuildVector(N0);
25121 if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode()))
25130 auto *BV0 = dyn_cast<BuildVectorSDNode>(N0);
25142 SDValue &S = (M < (int)NumElts ? N0 : N1);
25248 SDValue N0 = SVN->getOperand(0);
25255 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0));
25396 SDValue N0 = peekThroughBitcasts(SVN->getOperand(0));
25398 unsigned Opcode = N0.getOpcode();
25402 SDValue N00 = N0.getOperand(0);
25407 unsigned ExtDstSizeInBits = N0.getScalarValueSizeInBits();
25753 SDValue N0 = N->getOperand(0);
25756 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
25759 if (N0.isUndef() && N1.isUndef())
25765 if (N0 == N1)
25766 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
25770 if (N0.isUndef())
25786 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, NewMask);
25803 if (N0.hasOneUse() && TLI.isExtractVecEltCheap(VT, SplatIndex) &&
25804 TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) {
25807 SDValue L = N0.getOperand(0), R = N0.getOperand(1);
25814 DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags());
25823 N0.hasOneUse()) {
25824 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0)
25825 return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(0));
25827 if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT)
25828 if (auto *Idx = dyn_cast<ConstantSDNode>(N0.getOperand(2)))
25830 return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(1));
25834 if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() &&
25836 (N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR ||
25837 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) {
25838 EVT N00VT = N0.getOperand(0).getValueType();
25843 SDValue Op = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0),
25853 SDNode *V = N0.getNode();
25874 return N0;
25883 return N0;
25916 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
25920 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
25928 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() &&
25929 N0.getNumOperands() == 2 &&
25930 N0.getOperand(0) == N0.getOperand(1)) {
25942 SDValue UndefVec = DAG.getUNDEF(N0.getOperand(0).getValueType());
25944 N0.getOperand(0), UndefVec);
26003 if (SDValue InsertN1 = ShuffleToInsert(N0, N1, Mask))
26005 if (N0.getOpcode() == ISD::CONCAT_VECTORS) {
26008 if (SDValue InsertN0 = ShuffleToInsert(N1, N0, CommuteMask))
26034 (DemandedLHS.isZero() || DAG.MaskedVectorIsZero(N0, DemandedLHS)) &&
26056 VT, DAG.getVectorShuffle(IntVT, DL, DAG.getBitcast(IntVT, N0),
26061 VT, DAG.getNode(ISD::AND, DL, IntVT, DAG.getBitcast(IntVT, N0),
26076 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
26080 SDValue BC0 = peekThroughOneUseBitcasts(N0);
26163 // This shuffle index refers to the inner shuffle N0. Lookup the inner
26256 N0.getOpcode() != ISD::VECTOR_SHUFFLE) {
26264 bool HasSameOp0 = N0 == SV0;
26266 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
26273 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE &&
26275 cast<ShuffleVectorSDNode>(N0)->isSplat() &&
26315 unsigned SrcOpcode = N0.getOpcode();
26316 if (TLI.isBinOp(SrcOpcode) && N->isOnlyUserOf(N0.getNode()) &&
26320 SDValue Op00 = N0.getOperand(0);
26321 SDValue Op01 = N0.getOperand(1);
26336 SDValue InnerN = Commute ? N1 : N0;
26498 SDValue N0 = N->getOperand(0);
26505 return N0;
26510 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
26521 VT, N0, N1.getOperand(0), N2);
26531 // insert_subvector(N0, extract_subvector(N0, N2), N2) --> N0
26532 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && N1.getOperand(0) == N0 &&
26534 return N0;
26538 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR)
26546 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST &&
26558 // i.e. INSERT_SUBVECTOR (BITCAST N0) (BITCAST N1) N2 ->
26559 // BITCAST (INSERT_SUBVECTOR N0 N1 N2)
26560 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
26561 SDValue CN0 = N0.getOperand(0);
26577 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
26578 N0.getOperand(1).getValueType() == N1.getValueType() &&
26579 N0.getOperand(2) == N2)
26580 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0),
26586 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
26589 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
26595 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) &&
26597 SDValue N0Src = peekThroughBitcasts(N0);
26601 if ((N0.isUndef() || N0SrcSVT == N1SrcSVT) &&
26633 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() &&
26634 N1.getValueType() == N0.getOperand(1).getValueType()) {
26635 unsigned OtherIdx = N0.getConstantOperandVal(2);
26639 N0.getOperand(0), N1, N2);
26641 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N0.getNode()),
26642 VT, NewOp, N0.getOperand(1), N0.getOperand(2));
26648 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() &&
26649 N0.getOperand(0).getValueType() == N1.getValueType() &&
26650 N0.getOperand(0).getValueType().isScalableVector() ==
26653 SmallVector<SDValue, 8> Ops(N0->op_begin(), N0->op_end());
26666 SDValue N0 = N->getOperand(0);
26669 if (N0->getOpcode() == ISD::FP16_TO_FP)
26670 return N0->getOperand(0);
26679 SDValue N0 = N->getOperand(0);
26683 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) {
26684 ConstantSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1));
26686 return DAG.getNode(Op, SDLoc(N), N->getValueType(0), N0.getOperand(0));
26694 N->getValueType(0), {N0});
26699 SDValue N0 = N->getOperand(0);
26702 if (N0->getOpcode() == ISD::BF16_TO_FP)
26703 return N0->getOperand(0);
26714 SDValue N0 = N->getOperand(0);
26715 EVT VT = N0.getValueType();
26722 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getVectorElementType(), N0,
26736 DAG.ComputeNumSignBits(N0) == VT.getScalarSizeInBits())
26737 return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), N0);
26742 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
26743 TLI.isTypeLegal(N0.getOperand(1).getValueType())) {
26744 SDValue Vec = N0.getOperand(0);
26745 SDValue Subvec = N0.getOperand(1);
26747 (N0.getOperand(0).isUndef() || isNullOrNullSplat(Vec))) ||
26749 (N0.getOperand(0).isUndef() || isAllOnesOrAllOnesSplat(Vec))))
27017 SDValue N0 = N->getOperand(0);
27028 SDValue Src0 = DAG.getSplatSourceVector(N0, Index0);
27032 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR &&
27048 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode() &&
27049 count_if(N0->ops(), [](SDValue V) { return !V.isUndef(); }) == 1 &&
27069 SDValue N0 = N->getOperand(0);
27074 SDValue Src0 = DAG.getSplatSourceVector(N0, Index0);
27076 (N0.getOpcode() == ISD::SPLAT_VECTOR ||
27080 EVT SrcVT = N0.getValueType();
27210 SDValue DAGCombiner::SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1,
27212 assert(N0.getOpcode() == ISD::SETCC &&
27215 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
27216 cast<CondCodeSDNode>(N0.getOperand(2))->get());
27225 const SDNodeFlags Flags = N0->getFlags();
27226 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
27227 N0.getValueType(),
27434 /// Try to fold an expression of the form (N0 cond N1) ? N2 : N3 to a shift and
27436 SDValue DAGCombiner::foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0,
27443 EVT XType = N0.getValueType();
27454 if (!(isAllOnesConstant(N1) || (isNullConstant(N1) && N0 == N2)))
27459 if (!(isNullConstant(N1) || (isOneConstant(N1) && N0 == N2)))
27472 SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt);
27492 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt);
27508 SDValue N0 = N->getOperand(0);
27520 // TODO: Do we really need to check N0 (the condition operand of the select)?
27522 if (!N0->hasOneUse() || !N1->hasOneUse() || !N2->hasOneUse())
27534 SDValue NewSel = DAG.getSelect(DL, N10.getValueType(), N0, N10, N20);
27548 SDValue NewSel = DAG.getSelect(DL, N11.getValueType(), N0, N11, N21);
27563 SDValue N0 = N->getOperand(0);
27568 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse())
27571 SDValue Int = N0.getOperand(0);
27581 if (N0.getValueType().isVector()) {
27584 SignMask = APInt::getSignMask(N0.getScalarValueSizeInBits());
27594 SDLoc DL(N0);
27606 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
27608 if (!TLI.reduceSelectOfFPConstantLoads(N0.getValueType()))
27647 DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()), N0, N1, CC);
27658 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
27660 SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
27666 EVT CmpOpVT = N0.getValueType();
27674 if (SDValue SCC = DAG.FoldSetCC(CmpResVT, N0, N1, CC, DL)) {
27684 convertSelectOfFPConstantsToLoadOffset(DL, N0, N1, N2, N3, CC))
27687 if (SDValue V = foldSelectCCToShiftAnd(DL, N0, N1, N2, N3, CC))
27696 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
27697 N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
27698 SDValue AndLHS = N0->getOperand(0);
27699 auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
27707 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
27712 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
27741 SCC = DAG.getSetCC(DL, CmpResVT, N0, N1, CC);
27744 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
27781 // If the other operand is cttz/cttz_zero_undef of N0, and cttz is
27785 N0 == Count.getOperand(0) &&
27787 return DAG.getNode(ISD::CTTZ, DL, VT, N0);
27788 // If the other operand is ctlz/ctlz_zero_undef of N0, and ctlz is
27792 N0 == Count.getOperand(0) &&
27794 return DAG.getNode(ISD::CTLZ, DL, VT, N0);
27807 ISD::SRA, DL, CmpOpVT, N0,
27813 if (SDValue S = PerformMinMaxFpToSatCombine(N0, N1, N2, N3, CC, DAG))
27815 if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N2, N3, CC, DAG))
27822 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
27827 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);