Lines Matching defs:CC1
1273 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1.getOperand(2))->get();
1276 if (CC1 == CC00 && CC1 != CC01) {
1280 if (CC1 == CC01 && CC1 != CC00) {
5966 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
5968 if (LR == RR && CC0 == CC1 && IsInteger) {
5973 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
5975 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
5977 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
5979 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
5988 return DAG.getSetCC(DL, VT, Or, LR, CC1);
5992 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
5994 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
5996 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
5998 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
6007 return DAG.getSetCC(DL, VT, And, LR, CC1);
6013 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
6026 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
6030 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
6035 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
6039 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
6066 CC1 = ISD::getSetCCSwappedOperands(CC1);
6070 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
6071 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
6073 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT)
6074 : ISD::getSetCCOrOperation(CC0, CC1, OpVT);