Lines Matching defs:SU
104 for (const SUnit *SU : L) {
105 dbgs() << "SU(" << SU->NodeNum << ")";
106 if (SU != L.back())
236 /// MO is an operand of SU's instruction that defines a physical register. Adds
237 /// data dependencies from SU to any uses of the physical register.
238 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
239 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
248 const MCInstrDesc &DefMIDesc = SU->getInstr()->getDesc();
254 SUnit *UseSU = I->SU;
255 if (UseSU == SU)
265 Dep = SDep(SU, SDep::Artificial);
269 SU->hasPhysRegDefs = true;
277 Dep = SDep(SU, SDep::Data, UseReg);
280 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
285 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep, &SchedModel);
294 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
295 MachineInstr *MI = SU->getInstr();
314 SUnit *DefSU = I->SU;
319 if (DefSU != SU &&
321 SDep Dep(SU, Kind, DefMO.getReg());
326 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep,
334 SU->hasPhysRegUses = true;
339 Uses.insert(PhysRegSUOper(SU, OperIdx, Unit));
343 addPhysRegDataDeps(SU, OperIdx);
352 if (MO.isDead() && SU->isCall) {
364 if (!I->SU->isCall)
373 Defs.insert(PhysRegSUOper(SU, OperIdx, Unit));
404 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
405 MachineInstr *MI = SU->getInstr();
452 SUnit *UseSU = I->SU;
454 SDep Dep(SU, SDep::Data, Reg);
457 ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep,
490 SUnit *DefSU = V2SU.SU;
496 if (DefSU == SU)
498 SDep Dep(SU, SDep::Output, Reg);
508 V2SU.SU = SU;
515 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
524 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
525 const MachineInstr *MI = SU->getInstr();
534 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
543 if (V2SU.SU == SU)
546 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
587 SUnit *SU = newSUnit(&MI);
588 MISUnitMap[&MI] = SU;
590 SU->isCall = MI.isCall();
591 SU->isCommutable = MI.isCommutable();
593 // Assign the Latency field of SU using target-provided information.
594 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
605 const MCSchedClassDesc *SC = getSchedClass(SU);
611 SU->hasReservedResource = true;
614 SU->isUnbuffered = true;
639 /// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
641 void inline insert(SUnit *SU, ValueType V) {
642 MapVector::operator[](V).push_back(SU);
679 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
682 addChainDependencies(SU, I.second,
686 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
691 addChainDependencies(SU, Itr->second,
700 for (auto *SU : SUs)
701 SU->addPredBarrier(BarrierChain);
765 // objects. The SU is then inserted in the SUList(s) mapped from the
772 // Certain memory accesses are known to not alias any SU in Stores
827 SUnit *SU = MISUnitMap[&MI];
828 assert(SU && "No SUnit mapped to this MI");
838 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
862 addPhysRegDeps(SU, j);
865 addVRegDefDeps(SU, j);
879 addPhysRegDeps(SU, j);
881 addVRegUseDeps(SU, j);
891 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
892 SDep Dep(SU, SDep::Artificial);
893 Dep.setLatency(SU->Latency - 1);
906 BarrierChain->addPredBarrier(SU);
907 BarrierChain = SU;
909 LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
926 BarrierChain->addPredBarrier(SU);
928 FPExceptions.insert(SU, UnknownValue);
944 BarrierChain->addPredBarrier(SU);
948 // SU depends on.
956 addChainDependencies(SU, Stores);
957 addChainDependencies(SU, NonAliasStores);
958 addChainDependencies(SU, Loads);
959 addChainDependencies(SU, NonAliasLoads);
962 Stores.insert(SU, UnknownValue);
971 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
972 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
981 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
985 addChainDependencies(SU, Loads, UnknownValue);
986 addChainDependencies(SU, Stores, UnknownValue);
988 } else { // SU is a load.
991 addChainDependencies(SU, Stores);
992 addChainDependencies(SU, NonAliasStores);
994 Loads.insert(SU, UnknownValue);
1002 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
1005 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
1008 addChainDependencies(SU, Stores, UnknownValue);
1063 // Insert all SU's NodeNums into a vector and sort it.
1068 for (const auto *SU : SUs)
1069 NodeNums.push_back(SU->NodeNum);
1073 for (const auto *SU : SUs)
1074 NodeNums.push_back(SU->NodeNum);
1078 // The N last elements in NodeNums will be removed, and the SU with
1091 LLVM_DEBUG(dbgs() << "Inserting new barrier chain: SU("
1095 LLVM_DEBUG(dbgs() << "Keeping old barrier chain: SU("
1178 void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
1180 dumpNodeName(SU);
1182 dbgs() << " [TopReadyCycle = " << SU.TopReadyCycle
1183 << ", BottomReadyCycle = " << SU.BotReadyCycle << "]";
1185 SU.getInstr()->dump();
1193 for (const SUnit &SU : SUnits)
1194 dumpNodeAll(SU);
1200 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1203 if (SU == &EntrySU)
1205 else if (SU == &ExitSU)
1208 SU->getInstr()->print(oss, /*IsStandalone=*/true);
1273 bool isVisited(const SUnit *SU) const {
1274 return R.DFSNodeData[SU->NodeNum].SubtreeID
1280 void visitPreorder(const SUnit *SU) {
1281 R.DFSNodeData[SU->NodeNum].InstrCount =
1282 SU->getInstr()->isTransient() ? 0 : 1;
1288 void visitPostorderNode(const SUnit *SU) {
1291 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1292 RootData RData(SU->NodeNum);
1293 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1300 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1301 for (const SDep &PredDep : SU->Preds) {
1306 joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
1313 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1324 RootSet[SU->NodeNum] = RData;
1363 LLVM_DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1437 void follow(const SUnit *SU) {
1438 DFSStack.emplace_back(SU, SU->Preds.begin());
1458 static bool hasDataSucc(const SUnit *SU) {
1459 for (const SDep &SuccDep : SU->Succs) {
1474 for (const SUnit &SU : SUnits) {
1475 if (Impl.isVisited(&SU) || hasDataSucc(&SU))
1479 Impl.visitPreorder(&SU);
1480 DFS.follow(&SU);