Lines Matching defs:OperIdx

238 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
239   const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
249   bool ImplicitPseudoDef = (OperIdx >= DefMIDesc.getNumOperands() &&
280         Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
285       ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep, &SchedModel);
293 /// physical register referenced at OperIdx.
294 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
296   MachineOperand &MO = MI->getOperand(OperIdx);
324               SchedModel.computeOutputLatency(MI, OperIdx, DefInstr));
326         ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep,
339       Uses.insert(PhysRegSUOper(SU, OperIdx, Unit));
343     addPhysRegDataDeps(SU, OperIdx);
373       Defs.insert(PhysRegSUOper(SU, OperIdx, Unit));
400 /// the virtual register defined at OperIdx.
404 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
406   MachineOperand &MO = MI->getOperand(OperIdx);
424            llvm::drop_begin(MI->operands(), OperIdx + 1))
455         Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
457         ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep,
500       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
519 /// virtual register used at OperIdx is mapped to an SUnit. Add a register
524 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
528   const MachineOperand &MO = MI->getOperand(OperIdx);
534   CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));