Lines Matching defs:CP
245 bool joinIntervals(CoalescerPair &CP);
248 bool joinVirtRegs(CoalescerPair &CP);
256 bool joinReservedPhysReg(CoalescerPair &CP);
264 LaneBitmask LaneMask, CoalescerPair &CP,
270 LaneBitmask LaneMask, const CoalescerPair &CP);
276 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
291 std::pair<bool,bool> removeCopyByCommutingDef(const CoalescerPair &CP,
295 bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
299 bool reMaterializeTrivialDef(const CoalescerPair &CP, MachineInstr *CopyMI,
303 bool canJoinPhys(const CoalescerPair &CP);
371 void checkMergingChangesDbgValues(CoalescerPair &CP, LiveRange &LHS,
615 bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
617 assert(!CP.isPartial() && "This doesn't work for partial copies.");
618 assert(!CP.isPhys() && "This doesn't work for physreg copies.");
621 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
623 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
662 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
805 RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
807 assert(!CP.isPhys());
810 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
812 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
1088 bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
1090 assert(!CP.isPhys());
1104 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
1106 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
1287 bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
1291 Register SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
1292 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
1293 Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1294 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
1348 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(), DefSubIdx);
1382 const TargetRegisterClass *NewRC = CP.getNewRC();
1386 assert(SrcIdx == 0 && CP.isFlipped()
1907 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
1911 if (!MRI->isReserved(CP.getDstReg())) {
1916 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1974 CoalescerPair CP(*TRI);
1975 if (!CP.setRegisters(CopyMI)) {
1980 if (CP.getNewRC()) {
1981 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1982 auto DstRC = MRI->getRegClass(CP.getDstReg());
1983 unsigned SrcIdx = CP.getSrcIdx();
1984 unsigned DstIdx = CP.getDstIdx();
1985 if (CP.isFlipped()) {
1990 CP.getNewRC(), *LIS)) {
1999 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
2007 if (!CP.isPhys()) {
2020 if (CP.getSrcReg() == CP.getDstReg()) {
2021 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
2055 setUndefOnPrunedSubRegUses(LI, CP.getSrcReg(), PrunedLanes);
2065 if (CP.isPhys()) {
2067 << printReg(CP.getSrcReg(), TRI) << " with "
2068 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n');
2069 if (!canJoinPhys(CP)) {
2073 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
2081 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
2082 LIS->getInterval(CP.getDstReg()).size())
2083 CP.flip();
2087 << TRI->getRegClassName(CP.getNewRC()) << " with ";
2088 if (CP.getDstIdx() && CP.getSrcIdx())
2089 dbgs() << printReg(CP.getDstReg()) << " in "
2090 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "
2091 << printReg(CP.getSrcReg()) << " in "
2092 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';
2094 dbgs() << printReg(CP.getSrcReg(), TRI) << " in "
2095 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';
2106 if (!joinIntervals(CP)) {
2112 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
2117 if (!CP.isPartial() && !CP.isPhys()) {
2118 bool Changed = adjustCopiesBackFrom(CP, CopyMI);
2121 std::tie(Changed, Shrink) = removeCopyByCommutingDef(CP, CopyMI);
2125 Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
2137 if (!CP.isPartial() && !CP.isPhys())
2138 if (removePartialRedundancy(CP, *CopyMI))
2149 if (CP.isCrossClass()) {
2151 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
2156 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
2157 InflateRegs.push_back(CP.getDstReg());
2168 if (CP.getDstIdx())
2169 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
2170 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
2174 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
2186 // CP.getSrcReg()'s live interval has been merged into CP.getDstReg's live
2187 // interval. Since CP.getSrcReg() is in ToBeUpdated set and its live interval
2189 if (ToBeUpdated.count(CP.getSrcReg()))
2193 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
2199 LIS->removeInterval(CP.getSrcReg());
2202 TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
2205 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())
2206 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
2208 if (CP.isPhys())
2209 dbgs() << printReg(CP.getDstReg(), TRI);
2211 dbgs() << LIS->getInterval(CP.getDstReg());
2219 bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
2220 Register DstReg = CP.getDstReg();
2221 Register SrcReg = CP.getSrcReg();
2222 assert(CP.isPhys() && "Must be a physreg copy");
2266 if (CP.isFlipped()) {
2330 MRI->clearKillFlags(CP.getSrcReg());
2413 /// subregister SubIdx in the coalesced register. Either CP.DstIdx or
2414 /// CP.SrcIdx.
2431 const CoalescerPair &CP;
2595 NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
2909 if (CP.isCoalescable(DefMI)) {
2926 if (DefMI->isFullCopy() && !CP.isPartial() &&
3499 if (Reg.isVirtual() && Reg != CP.getSrcReg() && Reg != CP.getDstReg())
3516 const CoalescerPair &CP) {
3518 JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask,
3519 NewVNInfo, CP, LIS, TRI, true, true);
3520 JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask,
3521 NewVNInfo, CP, LIS, TRI, true, true);
3580 CoalescerPair &CP,
3585 [this, &Allocator, &ToMerge, &CP](LiveInterval::SubRange &SR) {
3591 joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);
3608 bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
3610 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
3611 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
3612 bool TrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(*CP.getNewRC());
3613 JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), LaneBitmask::getNone(),
3614 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3615 JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), LaneBitmask::getNone(),
3616 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3638 unsigned DstIdx = CP.getDstIdx();
3640 LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
3652 LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHS
3656 unsigned SrcIdx = CP.getSrcIdx();
3658 LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
3660 mergeSubRangeInto(LHS, RHS, Mask, CP, DstIdx);
3665 mergeSubRangeInto(LHS, R, Mask, CP, DstIdx);
3676 } else if (TrackSubRegLiveness && !CP.getDstIdx() && CP.getSrcIdx()) {
3678 CP.getNewRC()->getLaneMask(), LHS);
3679 mergeSubRangeInto(LHS, RHS, TRI->getSubRegIndexLaneMask(CP.getSrcIdx()), CP,
3680 CP.getDstIdx());
3702 checkMergingChangesDbgValues(CP, LHS, LHSVals, RHS, RHSVals);
3706 auto RegIt = RegToPHIIdx.find(CP.getSrcReg());
3731 if (CP.getSrcIdx() != 0 || CP.getDstIdx() != 0)
3734 if (PHIIt->second.SubReg && PHIIt->second.SubReg != CP.getSrcIdx())
3738 PHIIt->second.Reg = CP.getDstReg();
3742 if (CP.getSrcIdx() != 0)
3743 PHIIt->second.SubReg = CP.getSrcIdx();
3754 RegIt = RegToPHIIdx.find(CP.getDstReg());
3759 RegToPHIIdx.insert({CP.getDstReg(), InstrNums});
3789 bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
3790 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
3838 void RegisterCoalescer::checkMergingChangesDbgValues(CoalescerPair &CP,
3852 ScanForSrcReg(CP.getSrcReg());
3853 ScanForDstReg(CP.getDstReg());