Lines Matching defs:PhysReg
401 MCRegister PhysReg;
402 for (auto I = Order.begin(), E = Order.end(); I != E && !PhysReg; ++I) {
408 PhysReg = *I;
411 if (!PhysReg.isValid())
412 return PhysReg;
414 // PhysReg is available, but there may be a better choice.
439 uint8_t Cost = RegCosts[PhysReg];
443 return PhysReg;
445 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost "
448 return CheapReg ? CheapReg : PhysReg;
482 MCRegister PhysReg,
489 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
494 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
520 /// Returns true if the given \p PhysReg is a callee saved register and has not
522 bool RegAllocEvictionAdvisor::isUnusedCalleeSavedReg(MCRegister PhysReg) const {
523 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
527 return !Matrix->isPhysRegUsed(PhysReg);
558 MCRegister PhysReg) const {
559 if (RegCosts[PhysReg] >= CostPerUseLimit)
563 if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) {
565 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
566 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
765 if (Cand.PhysReg) {
817 // that all the through blocks have interference when PhysReg is unset.
1023 // - Candidate intervals can be assigned to Cand.PhysReg.
1094 RAGreedy::calculateRegionSplitCostAroundReg(MCPhysReg PhysReg,
1105 if (CandIndex == BestCand || !GlobalCand[CandIndex].PhysReg)
1122 Cand.reset(IntfCache, PhysReg);
1127 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
1130 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI)
1138 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1177 for (MCPhysReg PhysReg : Order) {
1178 assert(PhysReg);
1179 if (IgnoreCSR && EvictAdvisor->isUnusedCalleeSavedReg(PhysReg))
1182 calculateRegionSplitCostAroundReg(PhysReg, Order, BestCost, NumCands,
1206 LLVM_DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
1215 assert(!Cand.PhysReg && "Compact region has no physreg");
1485 /// in order to use PhysReg between two entries in SA->UseSlots.
1489 void RAGreedy::calcGapWeights(MCRegister PhysReg,
1505 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1540 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1657 for (MCPhysReg PhysReg : Order) {
1658 assert(PhysReg);
1660 // order to make use of PhysReg between UseSlots[I] and UseSlots[I + 1].
1661 calcGapWeights(PhysReg, GapWeight);
1664 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
1683 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore]
1810 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1811 if (PhysReg || !NewVRegs.empty())
1812 return PhysReg;
1825 MCRegister PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
1826 if (PhysReg || !NewVRegs.empty())
1827 return PhysReg;
1848 /// same, as \p PhysReg.
1851 MCRegister PhysReg,
1854 if (PhysReg == AssignedReg)
1856 return TRI.regsOverlap(PhysReg, AssignedReg);
1860 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
1861 /// recolored to free \p PhysReg.
1863 /// the live intervals that need to be recolored in order to free \p PhysReg
1868 MCRegister PhysReg, const LiveInterval &VirtReg,
1872 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1897 !assignedRegPartiallyOverlaps(*TRI, *VRM, PhysReg, *Intf)) &&
1989 for (MCRegister PhysReg : Order) {
1990 assert(PhysReg.isValid());
1992 << printReg(PhysReg, TRI) << '\n');
1997 if (Matrix->checkInterference(VirtReg, PhysReg) >
2005 // Early give up on this PhysReg if it is obvious we cannot recolor all
2007 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2014 // with VirtReg on PhysReg (or one of its aliases). Enqueue them for
2030 // Do as if VirtReg was assigned to PhysReg so that the underlying
2033 Matrix->assign(VirtReg, PhysReg);
2047 return PhysReg;
2051 << printReg(PhysReg, TRI) << '\n');
2075 MCRegister PhysReg;
2076 std::tie(LI, PhysReg) = RecolorStack[I];
2084 MCRegister PhysReg;
2085 std::tie(LI, PhysReg) = RecolorStack[I];
2087 Matrix->assign(*LI, PhysReg);
2114 MCRegister PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters,
2120 if (PhysReg == ~0u || (!PhysReg && !LI->empty()))
2123 if (!PhysReg) {
2130 << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
2132 Matrix->assign(*LI, PhysReg);
2175 const LiveInterval &VirtReg, AllocationOrder &Order, MCRegister PhysReg,
2182 return PhysReg;
2199 return PhysReg;
2205 return PhysReg;
2263 /// \p PhysReg was used.
2264 /// \return The cost of \p List for \p PhysReg.
2266 MCRegister PhysReg) {
2269 if (Info.PhysReg != PhysReg)
2285 // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
2286 // some register and PhysReg may be available for the other live-ranges.
2291 MCRegister PhysReg = VRM->getPhys(Reg);
2298 << '(' << printReg(PhysReg, TRI) << ")\n");
2320 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
2321 Matrix->checkInterference(LI, PhysReg)))
2332 if (CurrPhys != PhysReg) {
2335 BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg);
2349 Matrix->assign(LI, PhysReg);
2417 if (MCRegister PhysReg =
2423 EvictAdvisor->isUnusedCalleeSavedReg(PhysReg) && NewVRegs.empty()) {
2424 MCRegister CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
2431 return PhysReg;
2445 if (Register PhysReg =
2454 if (Hint && Hint != PhysReg)
2456 return PhysReg;
2474 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
2475 if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore))
2476 return PhysReg;