Lines Matching defs:Intf

505   for (const LiveInterval *Intf : Intfs) {
507     if (!VRM->hasPhys(Intf->reg()))
510     Matrix->unassign(*Intf);
511     assert((ExtraInfo->getCascade(Intf->reg()) < Cascade ||
512             VirtReg.isSpillable() < Intf->isSpillable()) &&
514     ExtraInfo->setCascade(Intf->reg(), Cascade);
516     NewVRegs.push_back(Intf->reg());
601 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
613     Intf.moveToBlock(BC.Number);
621     if (!Intf.hasInterference())
629       if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) {
632       } else if (Intf.first() < BI.FirstInstr) {
635       } else if (Intf.first() < BI.LastInstr) {
649       if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) {
652       } else if (Intf.last() > BI.LastInstr) {
655       } else if (Intf.last() > BI.FirstInstr) {
674 bool RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
682     Intf.moveToBlock(Number);
684     if (!Intf.hasInterference()) {
705     if (Intf.first() <= Indexes->getMBBStartIdx(Number))
711     if (Intf.last() >= SA->getLastSplitPoint(Number))
766       if (!addThroughConstraints(Cand.Intf, NewBlocks))
820   // The static split cost will be zero since Cand.Intf reports no interference.
822   if (!addSplitConstraints(Cand.Intf, Cost)) {
880     Cand.Intf.moveToBlock(BC.Number);
897       Cand.Intf.moveToBlock(Number);
898       if (Cand.Intf.hasInterference()) {
948         Cand.Intf.moveToBlock(Number);
949         IntfIn = Cand.Intf.first();
957         Cand.Intf.moveToBlock(Number);
958         IntfOut = Cand.Intf.last();
996         Cand.Intf.moveToBlock(Number);
997         IntfIn = Cand.Intf.first();
1004         Cand.Intf.moveToBlock(Number);
1005         IntfOut = Cand.Intf.last();
1126   if (!addSplitConstraints(Cand.Intf, Cost)) {
1847 /// Return true if the existing assignment of \p Intf overlaps, but is not the
1852                                          const LiveInterval &Intf) {
1853   MCRegister AssignedReg = VRM.getPhys(Intf.reg());
1883     for (const LiveInterval *Intf : reverse(Q.interferingVRegs())) {
1884       // If Intf is done and sits on the same register class as VirtReg, it
1888       // If VirtReg has tied defs and Intf doesn't, then
1895       if (((ExtraInfo->getStage(*Intf) == RS_Done &&
1896             MRI->getRegClass(Intf->reg()) == CurRC &&
1897             !assignedRegPartiallyOverlaps(*TRI, *VRM, PhysReg, *Intf)) &&
1899              !hasTiedDef(MRI, Intf->reg()))) ||
1900           FixedRegisters.count(Intf->reg())) {
1905       RecoloringCandidates.insert(Intf);