Lines Matching defs:PhysReg
203 MCPhysReg PhysReg = 0; ///< Currently held here.
279 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState);
280 bool isPhysRegFree(MCPhysReg PhysReg) const;
283 void markRegUsedInInstr(MCPhysReg PhysReg) {
284 for (MCRegUnit Unit : TRI->regunits(PhysReg))
289 bool isClobberedByRegMasks(MCPhysReg PhysReg) const {
290 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) {
291 return MachineOperand::clobbersPhysReg(Mask, PhysReg);
296 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const {
297 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
299 for (MCRegUnit Unit : TRI->regunits(PhysReg))
307 void markPhysRegUsedInInstr(MCPhysReg PhysReg) {
308 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
315 void unmarkRegUsedInInstr(MCPhysReg PhysReg) {
316 for (MCRegUnit Unit : TRI->regunits(PhysReg))
344 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
345 bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
346 bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
347 void freePhysReg(MCPhysReg PhysReg);
349 unsigned calcSpillCost(MCPhysReg PhysReg) const;
359 void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
376 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
386 MCPhysReg PhysReg);
449 void RegAllocFastImpl::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
450 for (MCRegUnit Unit : TRI->regunits(PhysReg))
454 bool RegAllocFastImpl::isPhysRegFree(MCPhysReg PhysReg) const {
455 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
624 /// Insert reload instruction for \p PhysReg before \p Before.
626 Register VirtReg, MCPhysReg PhysReg) {
628 << printReg(PhysReg, TRI) << '\n');
631 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);
671 MCPhysReg Reg = P.PhysReg;
684 MCPhysReg PhysReg = LR.PhysReg;
685 if (PhysReg == 0)
688 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin();
695 if (PrologLiveIns.count(PhysReg)) {
699 reload(MBB.begin(), LR.VirtReg, PhysReg);
701 reload(InsertBefore, LR.VirtReg, PhysReg);
723 /// Mark PhysReg as reserved or free after spilling any virtregs. This is very
726 bool RegAllocFastImpl::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) {
729 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
736 reload(ReloadBefore, VirtReg, LRI->PhysReg);
738 setPhysRegState(LRI->PhysReg, regFree);
739 LRI->PhysReg = 0;
755 void RegAllocFastImpl::freePhysReg(MCPhysReg PhysReg) {
756 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':');
758 MCRegister FirstUnit = *TRI->regunits(PhysReg).begin();
765 setPhysRegState(PhysReg, regFree);
771 setPhysRegState(LRI->PhysReg, regFree);
772 LRI->PhysReg = 0;
778 /// Return the cost of spilling clearing out PhysReg and aliases so it is free
779 /// for allocation. Returns 0 when PhysReg is free or disabled with all aliases
781 /// \returns spillImpossible when PhysReg or an alias can't be spilled.
782 unsigned RegAllocFastImpl::calcSpillCost(MCPhysReg PhysReg) const {
783 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
789 << printReg(PhysReg, TRI) << '\n');
836 /// This method updates local state so that we know that PhysReg is the
840 MCPhysReg PhysReg) {
843 << printReg(PhysReg, TRI) << '\n');
844 assert(LR.PhysReg == 0 && "Already assigned a physreg");
845 assert(PhysReg != 0 && "Trying to assign no register");
846 LR.PhysReg = PhysReg;
847 setPhysRegState(PhysReg, VirtReg);
849 assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
894 assert(LR.PhysReg == 0);
939 for (MCPhysReg PhysReg : AllocationOrder) {
940 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');
941 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) {
946 unsigned Cost = calcSpillCost(PhysReg);
950 assignVirtToPhysReg(MI, LR, PhysReg);
954 if (PhysReg == Hint0 || PhysReg == Hint1)
958 BestReg = PhysReg;
972 LR.PhysReg = 0;
988 MCPhysReg PhysReg;
989 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
990 PhysReg = LRI->PhysReg;
995 PhysReg = AllocationOrder[0];
1000 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx);
1003 MO.setReg(PhysReg);
1017 MCPhysReg PrevReg = LRI->PhysReg;
1022 LRI->PhysReg = 0;
1026 LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "
1030 .addReg(LRI->PhysReg, llvm::RegState::Kill);
1066 if (LRI->PhysReg == 0) {
1078 assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) &&
1082 << printReg(LRI->PhysReg, TRI) << '\n');
1085 MCPhysReg PhysReg = LRI->PhysReg;
1093 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
1103 TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI,
1106 Succ->addLiveIn(PhysReg);
1117 BundleVirtRegsMap[VirtReg] = PhysReg;
1119 markRegUsedInInstr(PhysReg);
1120 return setPhysReg(MI, MO, PhysReg);
1147 if (LRI->PhysReg == 0) {
1173 BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1175 markRegUsedInInstr(LRI->PhysReg);
1176 return setPhysReg(MI, MO, LRI->PhysReg);
1179 /// Changes operand OpNum in MI the refer the PhysReg, considering subregs.
1182 MCPhysReg PhysReg) {
1184 MO.setReg(PhysReg);
1190 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister());
1201 MI.addRegisterKilled(PhysReg, TRI, true);
1210 MI.addRegisterDead(PhysReg, TRI, true);
1212 MI.addRegisterDefined(PhysReg, TRI);
1244 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present");
1254 MCPhysReg PhysReg = LR.PhysReg;
1255 if (PhysReg != 0) {
1256 assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg");
1257 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1544 MCPhysReg PhysReg = LR.PhysReg;
1545 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg))
1546 displacePhysReg(MI, PhysReg);
1676 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1679 setPhysReg(MI, *RegMO, LRI->PhysReg);
1722 setPhysRegState(LiveReg.PhysReg, regPreAssigned);