Lines Matching defs:LRI

732       LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
733       assert(LRI != LiveVirtRegs.end() && "datastructures in sync");
736       reload(ReloadBefore, VirtReg, LRI->PhysReg);
738       setPhysRegState(LRI->PhysReg, regFree);
739       LRI->PhysReg = 0;
740       LRI->Reloaded = true;
768     LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
769     assert(LRI != LiveVirtRegs.end());
770     LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n');
771     setPhysRegState(LRI->PhysReg, regFree);
772     LRI->PhysReg = 0;
987   LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
989   if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
990     PhysReg = LRI->PhysReg;
1015   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
1016   if (LRI != LiveVirtRegs.end()) {
1017     MCPhysReg PrevReg = LRI->PhysReg;
1022       LRI->PhysReg = 0;
1023       allocVirtReg(MI, *LRI, 0, true);
1026       LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "
1030           .addReg(LRI->PhysReg, llvm::RegState::Kill);
1034       LRI->LastUse = &MI;
1053   LiveRegMap::iterator LRI;
1055   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1059         LRI->LiveOut = true;
1066   if (LRI->PhysReg == 0) {
1067     allocVirtReg(MI, *LRI, 0, LookAtPhysRegUses);
1068     // If no physical register is available for LRI, we assign one at random
1070     if (LRI->Error) {
1078     assert(!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) &&
1082                       << printReg(LRI->PhysReg, TRI) << '\n');
1085   MCPhysReg PhysReg = LRI->PhysReg;
1086   if (LRI->Reloaded || LRI->LiveOut) {
1090       LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut
1091                         << " RL: " << LRI->Reloaded << '\n');
1092       bool Kill = LRI->LastUse == nullptr;
1093       spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
1111       LRI->LastUse = nullptr;
1113     LRI->LiveOut = false;
1114     LRI->Reloaded = false;
1130   LiveRegMap::iterator LRI;
1132   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1136         LRI->LiveOut = true;
1143     assert((!MO.isKill() || LRI->LastUse == &MI) && "Invalid kill flag");
1147   if (LRI->PhysReg == 0) {
1160     allocVirtReg(MI, *LRI, Hint, false);
1161     if (LRI->Error) {
1170   LRI->LastUse = &MI;
1173     BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1175   markRegUsedInInstr(LRI->PhysReg);
1176   return setPhysReg(MI, MO, LRI->PhysReg);
1671     LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
1676     if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1679         setPhysReg(MI, *RegMO, LRI->PhysReg);