Lines Matching defs:MO
25 static bool isValidReg(const MachineOperand &MO) {
26 return MO.isReg() && MO.getReg();
29 static bool isValidRegUse(const MachineOperand &MO) {
30 return isValidReg(MO) && MO.isUse();
33 static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg,
35 if (!isValidRegUse(MO))
37 return TRI->regsOverlap(MO.getReg(), PhysReg);
40 static bool isValidRegDef(const MachineOperand &MO) {
41 return isValidReg(MO) && MO.isDef();
44 static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg,
46 if (!isValidRegDef(MO))
48 return TRI->regsOverlap(MO.getReg(), PhysReg);
128 for (auto &MO : MI->operands()) {
129 if (!isValidRegDef(MO))
131 for (MCRegUnit Unit : TRI->regunits(MO.getReg().asMCReg())) {
344 for (auto &MO : MI->operands()) {
345 if (!isValidRegUseOf(MO, PhysReg, TRI))
349 if (MO.isKill())
360 for (auto &MO : MI.operands()) {
361 if (!isValidRegUseOf(MO, PhysReg, TRI))
464 MachineOperand &MO) const {
465 assert(MO.isReg() && "Expected register operand");
466 return getUniqueReachingMIDef(MI, MO.getReg());
518 for (auto &MO : Last->operands())
519 if (isValidRegDefOf(MO, PhysReg, TRI))
538 for (auto &MO : Last->operands())
539 if (isValidRegDefOf(MO, PhysReg, TRI))
562 for (auto &MO : From->operands()) {
563 if (!isValidReg(MO))
565 if (MO.isDef())
566 Defs.insert(MO.getReg());
567 else if (!hasSameReachingDef(From, To, MO.getReg()))
577 for (auto &MO : I->operands())
578 if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg()))
630 for (auto &MO : MI->operands()) {
631 if (!isValidRegDef(MO))
635 getGlobalUses(MI, MO.getReg(), Uses);
656 for (auto &MO : Def->operands()) {
657 if (!isValidRegDef(MO))
659 if (!MO.isDead())
671 for (auto &MO : MI->operands()) {
672 if (!isValidRegUse(MO))
674 if (MachineInstr *Def = getMIOperand(MI, MO))
675 if (IsDead(Def, MO.getReg()))
706 for (auto &MO : I->operands())
707 if (isValidRegDefOf(MO, PhysReg, TRI))