Lines Matching refs:Def
185 /// Track Def -> Use info used for rewriting copies.
258 RegSubRegPair Def, RewriteMapTy &RewriteMap);
413 const MachineInstr *Def = nullptr;
415 /// The index of the definition in Def.
469 Def = MRI.getVRegDef(Reg);
714 /// retrieve all Def -> Use along the way up to the next source. Any found
754 // Insert the Def -> Use entry for the recently found source.
1167 /// Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
1169 /// multiple sources for a given \p Def are found along the way, we found a
1175 RegSubRegPair Def,
1178 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
1279 /// Rewrite the source found through \p Def, by using the \p RewriteMap
1286 RegSubRegPair Def, RewriteMapTy &RewriteMap) {
1287 assert(!Def.Reg.isPhysical() && "We do not rewrite physical registers");
1290 RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap);
1293 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
1301 if (Def.SubReg) {
1302 NewCopy->getOperand(0).setSubReg(Def.SubReg);
1309 MRI->replaceRegWith(Def.Reg, NewVReg);
1340 RegSubRegPair Def;
1342 while (CpyRewriter.getNextRewritableSource(Src, Def)) {
1345 if (Def.Reg.isPhysical())
1350 if (!findNextSource(Def, RewriteMap))
1353 RewritePairs.push_back(Def);
1357 for (const RegSubRegPair &Def : RewritePairs) {
1359 MachineInstr &NewCopy = rewriteSource(MI, Def, RewriteMap);
1732 const auto &Def = NAPhysToVirtMIs.find(Reg);
1733 if (Def != NAPhysToVirtMIs.end()) {
1738 NAPhysToVirtMIs.erase(Def);
1744 Register Def = RegMI.first;
1745 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1748 NAPhysToVirtMIs.erase(Def);
1883 assert(Def->isCopy() && "Invalid definition");
1884 // Copy instruction are supposed to be: Def = Src.
1888 assert(Def->getNumOperands() - Def->getNumImplicitOperands() == 2 &&
1890 assert(!Def->hasImplicitDef() && "Only implicit uses are allowed");
1892 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1897 const MachineOperand &Src = Def->getOperand(1);
1904 assert(Def->isBitcast() && "Invalid definition");
1907 if (Def->mayRaiseFPException() || Def->hasUnmodeledSideEffects())
1911 if (Def->getDesc().getNumDefs() != 1)
1913 const MachineOperand DefOp = Def->getOperand(DefIdx);
1919 unsigned SrcIdx = Def->getNumOperands();
1922 const MachineOperand &MO = Def->getOperand(OpIdx);
1935 // In some rare case, Def has no input, SrcIdx is out of bound,
1937 if (SrcIdx >= Def->getNumOperands())
1947 const MachineOperand &Src = Def->getOperand(SrcIdx);
1954 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1957 if (Def->getOperand(DefIdx).getSubReg())
1959 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1963 // Def.sub0 =
1964 // Def.sub1 =
1965 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1966 // Def. Thus, it must not be generated.
1968 // Def.sub0 (i.e, not defining the other subregs) and we would
1980 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1984 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1998 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
2001 if (Def->getOperand(DefIdx).getSubReg())
2014 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
2018 // Def = INSERT_SUBREG v0, v1, sub1
2030 const MachineOperand &MODef = Def->getOperand(DefIdx);
2031 // If the result register (Def) and the base register (v0) do not
2046 // we used for Def.
2051 assert((Def->isExtractSubreg() ||
2052 Def->isExtractSubregLike()) && "Invalid definition");
2054 // Def = EXTRACT_SUBREG v0, sub0
2067 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
2080 assert(Def->isSubregToReg() && "Invalid definition");
2082 // Def = SUBREG_TO_REG Imm, v0, sub0
2088 if (DefSubReg != Def->getOperand(3).getImm())
2092 if (Def->getOperand(2).getSubReg())
2095 return ValueTrackerResult(Def->getOperand(2).getReg(),
2096 Def->getOperand(3).getImm());
2101 assert(Def->isPHI() && "Invalid definition");
2106 if (Def->getOperand(0).getSubReg() != DefSubReg)
2110 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
2111 const MachineOperand &MO = Def->getOperand(i);
2124 assert(Def && "This method needs a valid definition");
2126 assert(((Def->getOperand(DefIdx).isDef() &&
2127 (DefIdx < Def->getDesc().getNumDefs() ||
2128 Def->getDesc().isVariadic())) ||
2129 Def->getOperand(DefIdx).isImplicit()) &&
2131 if (Def->isCopy())
2133 if (Def->isBitcast())
2139 if (Def->isRegSequence() || Def->isRegSequenceLike())
2141 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
2143 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
2145 if (Def->isSubregToReg())
2147 if (Def->isPHI())
2155 if (!Def)
2168 Res.setInst(Def);
2175 Def = DI->getParent();
2179 Def = nullptr;
2187 Def = nullptr;