Lines Matching +full:non +full:- +full:live
1 //===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // Register live intervals: Registers must be defined only once, and must be
19 // The machine code verifier is enabled with the command-line option
20 // -verify-machineinstrs.
21 //===----------------------------------------------------------------------===//
144 // Add Reg and any sub-registers to RV
148 append_range(RV, TRI->subregs(Reg.asMCReg()));
155 // Vregs that must be live in because they are used without being
164 // Regs defined in MBB and live out. Note that vregs passing through may
165 // be live out without being mentioned here.
207 // Live-out registers are either in regsLiveOut or vregsPassed.
221 return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
407 for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
408 E = Indexes->MBBIndexEnd(); I != E; ++I) {
409 assert(!Last.isValid() || I->first > Last);
410 Last = I->first;
420 MRI->getNumVirtRegs())
427 this->MF = &MF;
437 // If we're mid-GlobalISel and we already triggered the fallback path then
451 auto *LISWrapper = PASS->getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
452 LiveInts = LISWrapper ? &LISWrapper->getLIS() : nullptr;
454 auto *LVWrapper = PASS->getAnalysisIfAvailable<LiveVariablesWrapperPass>();
456 LiveVars = LVWrapper ? &LVWrapper->getLV() : nullptr;
457 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
458 auto *SIWrapper = PASS->getAnalysisIfAvailable<SlotIndexesWrapperPass>();
459 Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
463 LiveInts = MFAM->getCachedResult<LiveIntervalsAnalysis>(Func);
465 LiveVars = MFAM->getCachedResult<LiveVariablesAnalysis>(Func);
466 // TODO: LiveStks = MFAM->getCachedResult<LiveStacksAnalysis>(Func);
467 Indexes = MFAM->getCachedResult<SlotIndexesAnalysis>(Func);
548 LiveInts->print(errs());
550 MF->print(errs(), Indexes);
553 << "- function: " << MF->getName() << "\n";
558 report(msg, MBB->getParent());
559 errs() << "- basic block: " << printMBBReference(*MBB) << ' '
560 << MBB->getName() << " (" << (const void *)MBB << ')';
562 errs() << " [" << Indexes->getMBBStartIdx(MBB)
563 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
569 report(msg, MI->getParent());
570 errs() << "- instruction: ";
571 if (Indexes && Indexes->hasIndex(*MI))
572 errs() << Indexes->getInstructionIndex(*MI) << '\t';
573 MI->print(errs(), /*IsStandalone=*/true);
579 report(msg, MO->getParent());
580 errs() << "- operand " << MONum << ": ";
581 MO->print(errs(), MOVRegType, TRI);
590 errs() << "- at: " << Pos << '\n';
594 errs() << "- interval: " << LI << '\n';
606 errs() << "- segment: " << S << '\n';
610 errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
614 errs() << "- liverange: " << LR << '\n';
618 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
622 errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
629 errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
634 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
641 for (const MachineBasicBlock *Succ : MBB->successors())
648 regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
649 : TRI->getReservedRegs(*MF);
651 if (!MF->empty())
652 markReachable(&MF->front());
670 MRI->verifyUseLists();
672 if (!MF->empty())
681 if (!MF->getProperties().hasProperty(
682 MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
683 // If this block has allocatable physical registers live-in, check that
685 for (const auto &LI : MBB->liveins()) {
686 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
687 MBB->getIterator() != MBB->getParent()->begin() &&
688 !MBB->isInlineAsmBrIndirectTarget()) {
689 report("MBB has allocatable live-in, but isn't entry, landing-pad, or "
690 "inlineasm-br-indirect-target.",
697 if (MBB->isIRBlockAddressTaken()) {
698 if (!MBB->getAddressTakenIRBlock()->hasAddressTaken())
699 report("ir-block-address-taken is associated with basic block not used by "
706 for (const auto *succ : MBB->successors()) {
707 if (succ->isEHPad())
719 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
729 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
730 const BasicBlock *BB = MBB->getBasicBlock();
731 const Function &F = MF->getFunction();
734 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
735 BB && isa<SwitchInst>(BB->getTerminator())) &&
742 if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
748 if (!MBB->empty() && MBB->back().isBarrier() &&
749 !TII->isPredicated(MBB->back())) {
750 report("MBB exits via unconditional fall-through but ends with a "
754 report("MBB exits via unconditional fall-through but has a condition!",
759 if (MBB->empty()) {
762 } else if (!MBB->back().isBarrier()) {
765 } else if (!MBB->back().isTerminator()) {
771 if (MBB->empty()) {
772 report("MBB exits via conditional branch/fall-through but doesn't "
774 } else if (MBB->back().isBarrier()) {
775 report("MBB exits via conditional branch/fall-through but ends with a "
777 } else if (!MBB->back().isTerminator()) {
778 report("MBB exits via conditional branch/fall-through but the branch "
784 if (MBB->empty()) {
787 } else if (!MBB->back().isBarrier()) {
790 } else if (!MBB->back().isTerminator()) {
804 if (TBB && !MBB->isSuccessor(TBB))
808 if (FBB && !MBB->isSuccessor(FBB))
822 MachineFunction::const_iterator MBBI = std::next(MBB->getIterator());
823 if (MBBI == MF->end()) {
825 } else if (!MBB->isSuccessor(&*MBBI))
826 report("MBB exits via conditional branch/fall-through but the CFG "
831 // Verify that there aren't any extra un-accounted-for successors.
832 for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
838 if (Fallthrough && SuccMBB == MBB->getNextNode())
840 // Also accept successors which are for exception-handling or might be
842 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
851 if (MRI->tracksLiveness()) {
852 for (const auto &LI : MBB->liveins()) {
854 report("MBB live-in list contains non-physical register", MBB);
857 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
862 const MachineFrameInfo &MFI = MF->getFrameInfo();
865 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
873 lastIndex = Indexes->getMBBStartIdx(MBB);
877 // stand-alone unbundled instructions.
879 if (Indexes && Indexes->hasIndex(*MI)) {
880 SlotIndex idx = Indexes->getInstructionIndex(*MI);
888 // Ensure non-terminators don't follow terminators.
889 if (MI->isTerminator()) {
894 // precede non-terminators.
895 if (FirstTerminator->getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
896 report("Non-terminator instruction after the first terminator", MI);
906 if (MI->getNumOperands() < 2) {
910 if (!MI->getOperand(0).isSymbol())
912 if (!MI->getOperand(1).isImm())
917 if (!isUInt<6>(MI->getOperand(1).getImm()))
918 report("Unknown asm flags", &MI->getOperand(1), 1);
924 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
925 const MachineOperand &MO = MI->getOperand(OpNo);
933 if (OpNo > MI->getNumOperands())
937 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
941 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
942 const MachineOperand &MO = MI->getOperand(OpNo);
947 if (MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
948 const MachineBasicBlock *MBB = MI->getParent();
950 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
952 const MachineOperand &MO = MI->getOperand(i);
965 if (!MBB->isSuccessor(IndirectTargetMBB))
969 if (!IndirectTargetMBB->isPredecessor(MBB))
997 report("operand types must be all-vector or all-scalar", MI);
1015 auto Opcode = MI->getOpcode();
1018 unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
1021 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
1024 report(Twine(TII->getName(Opcode),
1030 report(Twine(TII->getName(Opcode), " used with readnone intrinsic"), MI);
1039 auto Opcode = MI->getOpcode();
1042 unsigned IntrID = cast<GIntrinsic>(MI)->getIntrinsicID();
1045 MF->getFunction().getContext(), static_cast<Intrinsic::ID>(IntrID));
1048 report(Twine(TII->getName(Opcode), " used with a convergent intrinsic"),
1054 Twine(TII->getName(Opcode), " used with a non-convergent intrinsic"),
1067 const MCInstrDesc &MCID = MI->getDesc();
1068 unsigned NumOps = MI->getNumOperands();
1071 if (MI->isBranch() && !MI->isIndirectBranch()) {
1073 for (const MachineOperand &Op : MI->operands()) {
1098 const MachineOperand *MO = &MI->getOperand(I);
1099 if (!MO->isReg()) {
1104 LLT OpTy = MRI->getType(MO->getReg());
1121 for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
1122 const MachineOperand *MO = &MI->getOperand(I);
1123 if (MO->isReg() && MO->getReg().isPhysical())
1128 if (MI->getNumOperands() < MCID.getNumOperands())
1132 if (!TII->verifyInstruction(*MI, ErrorInfo))
1136 unsigned Opc = MI->getOpcode();
1142 if (!MI->getOperand(2).isImm()) {
1147 Register Dst = MI->getOperand(0).getReg();
1148 Register Src = MI->getOperand(1).getReg();
1149 LLT SrcTy = MRI->getType(Src);
1150 int64_t Imm = MI->getOperand(2).getImm();
1161 const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI);
1162 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI);
1170 // Don't allow a class change. Do allow member class->regbank.
1171 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst);
1172 if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) {
1184 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1188 if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1189 if (!MI->getOperand(1).isCImm()) {
1194 const ConstantInt *CI = MI->getOperand(1).getCImm();
1195 if (CI->getBitWidth() != DstTy.getSizeInBits())
1198 if (!MI->getOperand(1).isFPImm()) {
1202 const ConstantFP *CF = MI->getOperand(1).getFPImm();
1204 if (APFloat::getSizeInBits(CF->getValueAPF().getSemantics()) !=
1216 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1217 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1223 if (!MI->hasOneMemOperand()) {
1227 const MachineMemOperand &MMO = **MI->memoperands_begin();
1228 if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1229 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1233 } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1237 } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1259 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1260 if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1264 LLT Ty = MRI->getType(MO.getReg());
1275 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1276 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1294 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1295 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1304 if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1309 } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1315 assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1327 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1328 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1329 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1340 const DataLayout &DL = MF->getDataLayout();
1353 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1354 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1355 LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1380 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1381 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1392 switch (MI->getOpcode()) {
1407 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1408 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1422 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1423 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1427 const unsigned NumOps = MI->getNumOperands();
1428 if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1432 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1439 unsigned NumDsts = MI->getNumOperands() - 1;
1440 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1442 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy) {
1448 LLT SrcTy = MRI->getType(MI->getOperand(NumDsts).getReg());
1478 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1479 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1488 if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1491 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1492 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1500 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1501 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1505 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1506 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1518 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1519 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1524 if (MI->getNumOperands() < 3)
1527 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1528 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1531 SrcTy.getElementCount() * (MI->getNumOperands() - 1))
1537 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1538 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1549 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1550 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1551 LLT SrcTy2 = MRI->getType(MI->getOperand(2).getReg());
1578 const MachineOperand &SrcOp = MI->getOperand(1);
1584 const MachineOperand &OffsetOp = MI->getOperand(2);
1590 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1591 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1600 const MachineOperand &SrcOp = MI->getOperand(2);
1606 const MachineOperand &OffsetOp = MI->getOperand(3);
1612 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1613 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1624 if (!MI->getOperand(1).isJTI())
1626 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1632 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1635 if (!MI->getOperand(1).isJTI())
1638 const auto &IdxOp = MI->getOperand(2);
1639 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1649 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1663 if (!MI->getOperand(2).isImm()) {
1668 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1669 int64_t Imm = MI->getOperand(2).getImm();
1677 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1683 if (!MI->getOperand(1).isCImm()) {
1687 if (MI->getOperand(1).getCImm()->isZero()) {
1694 const MachineOperand &Src0Op = MI->getOperand(1);
1700 const MachineOperand &Src1Op = MI->getOperand(2);
1706 const MachineOperand &IndexOp = MI->getOperand(3);
1712 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1713 LLT Src0Ty = MRI->getType(Src0Op.getReg());
1714 LLT Src1Ty = MRI->getType(Src1Op.getReg());
1751 const MachineOperand &SrcOp = MI->getOperand(1);
1757 const MachineOperand &IndexOp = MI->getOperand(2);
1763 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1764 LLT SrcTy = MRI->getType(SrcOp.getReg());
1792 const MachineOperand &MaskOp = MI->getOperand(3);
1798 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1799 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1800 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1830 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1831 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1854 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1855 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1856 LLT IdxTy = MRI->getType(MI->getOperand(2).getReg());
1868 auto TLI = MF->getSubtarget().getTargetLowering();
1870 TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
1878 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1879 LLT VecTy = MRI->getType(MI->getOperand(1).getReg());
1880 LLT ScaTy = MRI->getType(MI->getOperand(2).getReg());
1881 LLT IdxTy = MRI->getType(MI->getOperand(3).getReg());
1898 auto TLI = MF->getSubtarget().getTargetLowering();
1900 TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
1908 const MachineOperand &DstOp = MI->getOperand(0);
1909 const MachineOperand &AllocOp = MI->getOperand(1);
1910 const MachineOperand &AlignOp = MI->getOperand(2);
1912 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1917 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1931 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1937 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1938 (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1943 if (MMOs[0]->getSize() != MMOs[1]->getSize())
1946 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1947 LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1954 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1956 if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1960 if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1967 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1974 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1979 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1985 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1988 if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1989 (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1995 const MachineOperand &KindOp = MI->getOperand(0);
1996 if (!MI->getOperand(0).isImm()) {
2000 int64_t Kind = MI->getOperand(0).getImm();
2007 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2008 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
2009 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
2033 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2041 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
2053 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
2054 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
2069 LLT DestTy = MRI->getType(MI->getOperand(0).getReg());
2075 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
2083 const MachineOperand &TestMO = MI->getOperand(2);
2085 report("floating-point class set (operand 2) must be an immediate", MI);
2090 report("Incorrect floating-point class set (operand 2)", MI);
2096 const MachineOperand &AddrOp = MI->getOperand(0);
2097 if (!AddrOp.isReg() || !MRI->getType(AddrOp.getReg()).isPointer()) {
2101 const MachineOperand &RWOp = MI->getOperand(1);
2103 report("rw operand must be an immediate 0-1", &RWOp, 1);
2106 const MachineOperand &LocalityOp = MI->getOperand(2);
2108 report("locality operand must be an immediate 0-3", &LocalityOp, 2);
2111 const MachineOperand &CacheTypeOp = MI->getOperand(3);
2113 report("cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
2119 if (MI->getOperand(2).getImm() < 1)
2124 if (!MI->getOperand(1).isCPI())
2126 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
2131 const MachineOperand &AddrOp = MI->getOperand(1);
2132 if (!AddrOp.isReg() || !MRI->getType(AddrOp.getReg()).isPointer())
2142 const MCInstrDesc &MCID = MI->getDesc();
2143 if (MI->getNumOperands() < MCID.getNumOperands()) {
2146 << MI->getNumOperands() << " given.\n";
2149 if (MI->getFlag(MachineInstr::NoConvergent) && !MCID.isConvergent())
2152 if (MI->isPHI()) {
2153 if (MF->getProperties().hasProperty(
2158 report("Found PHI instruction after non-PHI", MI);
2163 if (MI->isInlineAsm())
2167 if (TII->isUnspillableTerminator(MI)) {
2168 if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
2170 Register Def = MI->getOperand(0).getReg();
2172 !MF->getProperties().hasProperty(
2174 std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
2178 // A fully-formed DBG_VALUE must have a location. Ignore partially formed
2181 if (MI->isDebugValue() && MI->getNumOperands() == 4)
2182 if (!MI->getDebugLoc())
2187 if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
2191 for (MachineMemOperand *Op : MI->memoperands()) {
2192 if (Op->isLoad() && !MI->mayLoad())
2194 if (Op->isStore() && !MI->mayStore())
2201 bool mapped = !LiveInts->isNotInMIMap(*MI);
2202 if (MI->isDebugOrPseudoInstr()) {
2205 } else if (MI->isInsideBundle()) {
2221 if (!TII->verifyInstruction(*MI, ErrorInfo))
2225 switch (MI->getOpcode()) {
2227 const MachineOperand &DstOp = MI->getOperand(0);
2228 const MachineOperand &SrcOp = MI->getOperand(1);
2232 LLT DstTy = MRI->getType(DstReg);
2233 LLT SrcTy = MRI->getType(SrcReg);
2249 TypeSize SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
2250 TypeSize DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
2253 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2255 SrcSize = TRI->getRegSizeInBits(*SrcRC);
2260 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2262 DstSize = TRI->getRegSizeInBits(*DstRC);
2290 if (!MI->getOperand(SO.getIDPos()).isImm() ||
2291 !MI->getOperand(SO.getNBytesPos()).isImm() ||
2292 !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
2298 if (Offset >= MI->getNumOperands()) {
2302 if (!MI->getOperand(Offset - 1).isImm() ||
2303 MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
2304 !MI->getOperand(Offset).isImm())
2317 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2318 for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
2320 if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
2325 report("STATEPOINT def tied to non-gc operand", MI);
2334 if (unsigned SubIdx = MI->getOperand(2).getSubReg())
2335 InsertedSize = TRI->getSubRegIdxSize(SubIdx);
2337 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
2338 unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
2346 unsigned NumOps = MI->getNumOperands();
2353 const MachineOperand &RegOp = MI->getOperand(I);
2354 const MachineOperand &SubRegOp = MI->getOperand(I + 1);
2360 SubRegOp.getImm() >= TRI->getNumSubRegIndices()) {
2366 Register DstReg = MI->getOperand(0).getReg();
2370 if (MI->getOperand(0).getSubReg())
2380 const MachineInstr *MI = MO->getParent();
2381 const MCInstrDesc &MCID = MI->getDesc();
2384 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
2389 if (!MO->isReg())
2391 else if (!MO->isDef() && !MCOI.isOptionalDef())
2393 else if (MO->isImplicit())
2398 // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
2399 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
2401 if (MO->isReg()) {
2402 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
2404 if (MO->isImplicit())
2410 !MO->isReg() && !MO->isFI())
2412 if (MO->isReg()) {
2415 !TII->isPCRelRegisterOperandLegal(*MO)))
2416 report("Expected a non-register operand.", MO, MONum);
2421 if (TiedTo != -1) {
2422 if (!MO->isReg())
2424 else if (!MO->isTied())
2426 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
2428 else if (MO->getReg().isPhysical()) {
2429 const MachineOperand &MOTied = MI->getOperand(TiedTo);
2433 MO->getReg() != MOTied.getReg())
2436 } else if (MO->isReg() && MO->isTied())
2438 } else if (!MI->isVariadic()) {
2440 if (!MO->isValidExcessOperand())
2441 report("Extra explicit operand on non-variadic instruction", MO, MONum);
2444 switch (MO->getType()) {
2448 if (MI->isDebugInstr() && MO->isUse()) {
2449 if (!MO->isDebug())
2451 } else if (MO->isDebug()) {
2455 const Register Reg = MO->getReg();
2458 if (MRI->tracksLiveness() && !MI->isDebugInstr())
2461 if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
2462 MO->getReg().isVirtual()) // TODO: Apply to physregs too
2466 if (MO->isTied()) {
2467 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
2468 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
2473 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
2477 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
2487 // Verify two-address constraints after the twoaddressinstruction pass.
2488 // Both twoaddressinstruction pass and phi-node-elimination pass call
2489 // MRI->leaveSSA() to set MF as not IsSSA, we should do the verification
2490 // after twoaddressinstruction pass not after phi-node-elimination pass. So
2492 // TiedOpsRewritten property to verify two-address constraints, this
2495 if (MF->getProperties().hasProperty(
2497 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2498 Reg != MI->getOperand(DefIdx).getReg())
2499 report("Two-address instruction operands must be identical", MO, MONum);
2502 unsigned SubIdx = MO->getSubReg();
2511 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2512 if (!DRC->contains(Reg)) {
2515 << TRI->getRegClassName(DRC) << " register.\n";
2519 if (MO->isRenamable()) {
2520 if (MRI->isReserved(Reg)) {
2527 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
2537 if (MO->isUndef())
2545 if (isFunctionTracksDebugUserValues || !MO->isUse() ||
2546 !MI->isDebugValue() || !MRI->def_empty(Reg)) {
2547 // If we're post-Select, we can't have gvregs anymore.
2555 LLT Ty = MRI->getType(Reg);
2562 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
2563 const RegisterBankInfo *RBI = MF->getSubtarget().getRegBankInfo();
2565 // If we're post-RegBankSelect, the gvreg must have a bank.
2575 RBI->getMaximumSize(RegBank->getID()) < Ty.getSizeInBits()) {
2578 errs() << "Register bank " << RegBank->getName() << " too small("
2579 << RBI->getMaximumSize(RegBank->getID()) << ") to fit "
2580 << Ty.getSizeInBits() << "-bits\n";
2596 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2600 << TRI->getRegClassName(
2601 TII->getRegClass(MCID, MONum, TRI, *MF))
2610 TRI->getSubClassWithSubReg(RC, SubIdx);
2613 errs() << "Register class " << TRI->getRegClassName(RC)
2619 errs() << "Register class " << TRI->getRegClassName(RC)
2626 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2629 TRI->getLargestLegalSuperClass(RC, *MF);
2634 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2636 report("No matching super-reg register class.", MO, MONum);
2640 if (!RC->hasSuperClassEq(DRC)) {
2642 errs() << "Expected a " << TRI->getRegClassName(DRC)
2643 << " register, but got a " << TRI->getRegClassName(RC)
2653 regMasks.push_back(MO->getRegMask());
2657 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2662 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2663 LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2664 int FI = MO->getIndex();
2665 LiveInterval &LI = LiveStks->getInterval(FI);
2666 SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2668 bool stores = MI->mayStore();
2669 bool loads = MI->mayLoad();
2670 // For a memory-to-memory move, we need to check if the frame
2674 for (auto *MMO : MI->memoperands()) {
2675 const PseudoSourceValue *PSV = MMO->getPseudoValue();
2680 if (Value->getFrameIndex() != FI) continue;
2682 if (MMO->isStore())
2693 errs() << "Live stack: " << LI << '\n';
2697 errs() << "Live stack: " << LI << '\n';
2703 if (MO->getCFIIndex() >= MF->getFrameInstructions().size())
2717 const MachineInstr *MI = MO->getParent();
2719 bool HasValue = LRQ.valueIn() || (MI->isPHI() && LRQ.valueOut());
2721 // live subregister range, the others may be dead.
2723 report("No live segment at use", MO, MONum);
2728 if (MO->isKill() && !LRQ.isKill()) {
2729 report("Live range continues after kill flag", MO, MONum);
2751 // Check that there is an early-clobber def of the same superregister
2753 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) ||
2754 !SlotIndex::isSameInstr(VNI->def, DefIdx) ||
2755 (VNI->def != DefIdx &&
2756 (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) {
2757 report("Inconsistent valno->def", MO, MONum);
2766 report("No live segment at def", MO, MONum);
2774 if (MO->isDead()) {
2779 // could be other non-dead defs of other subregs, or we could have other
2780 // parts of the register being live through the instruction. So unless we
2781 // are checking liveness for a subrange it is ok for the live range to
2783 if (SubRangeCheck || MO->getSubReg() == 0) {
2784 report("Live range continues after dead def flag", MO, MONum);
2795 const MachineInstr *MI = MO->getParent();
2796 const Register Reg = MO->getReg();
2797 const unsigned SubRegIdx = MO->getSubReg();
2801 if (LiveInts->hasInterval(Reg)) {
2802 LI = &LiveInts->getInterval(Reg);
2803 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
2804 !LI->hasSubRanges() && MRI->shouldTrackSubRegLiveness(Reg))
2805 report("Live interval for subreg operand has no subranges", MO, MONum);
2807 report("Virtual register has no live interval", MO, MONum);
2812 if (MO->readsReg()) {
2813 if (MO->isKill())
2819 if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2820 !MI->isBundledWithPred()) {
2821 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2827 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2829 if (MI->isPHI()) {
2830 // PHI use occurs on the edge, so check for live out here instead.
2831 UseIdx = LiveInts->getMBBEndIdx(
2832 MI->getOperand(MONum + 1).getMBB()).getPrevSlot();
2834 UseIdx = LiveInts->getInstructionIndex(*MI);
2838 for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg())) {
2839 if (MRI->isReservedRegUnit(Unit))
2841 if (const LiveRange *LR = LiveInts->getCachedRegUnit(Unit))
2850 if (LI->hasSubRanges() && !MO->isDef()) {
2852 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2853 : MRI->getMaxLaneMaskForVReg(Reg);
2855 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2860 if (LRQ.valueIn() || (MI->isPHI() && LRQ.valueOut()))
2863 // At least parts of the register has to be live at the use.
2865 report("No live subrange at use", MO, MONum);
2869 // For PHIs all lanes should be live
2870 if (MI->isPHI() && LiveInMask != MOMask) {
2871 report("Not all lanes of PHI source live at use", MO, MONum);
2887 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2894 // If there is an additional implicit-use of a super register we stop
2899 for (const MachineOperand &MOP : MI->uses()) {
2906 if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2912 } else if (MRI->def_empty(Reg)) {
2915 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2916 // We don't know which virtual registers are live in, so only complain
2918 // must be live in. PHI instructions are handled separately.
2921 else if (!MI->isPHI())
2927 if (MO->isDef()) {
2930 if (MO->isDead())
2936 if (MRI->isSSA() && Reg.isVirtual() &&
2937 std::next(MRI->def_begin(Reg)) != MRI->def_end())
2940 // Check LiveInts for a live segment, but only for virtual registers.
2941 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2942 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2943 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2948 if (LI->hasSubRanges()) {
2950 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2951 : MRI->getMaxLaneMaskForVReg(Reg);
2952 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2965 // Normal stand-alone instructions are also considered 'bundles', and this
2968 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2989 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
3041 // and pays easily for double look-ups (even in Dense with SparseUniverseMax
3062 // number of very sparse VRegFilter instances live at the same time). In
3063 // practice even in the worst-by-execution time cases having all elements
3066 // worst-case memory usage within 2x of figures determined empirically for
3067 // "all Dense" scenario in such worst-by-execution-time cases.
3072 // Implements both a transfer function and a (binary, in-place) join operator
3074 // (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
3083 // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
3091 // Double-duty the Filter: to maintain VRegs a set (and the join operation
3103 // can pass through an MBB live, but may not be live every time. It is assumed
3106 if (MF->empty())
3118 for (const MachineBasicBlock *Pred : MB->predecessors()) {
3135 // First push live-in regs to predecessors' vregsRequired.
3169 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3229 report("PHI operand is not live-out from predecessor", &MO0, I);
3278 // Check for killed virtual registers that should be live out.
3283 report("Virtual register killed in block, but needed live out.", &MBB);
3289 if (!MF->empty()) {
3290 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3302 // Check live-in list of each MBB. If a register is live into MBB, check
3304 // this must come from a definition in the predecesssor or its live-in
3305 // list, this will catch a live-through case where the predecessor does not
3306 // have the register in its live-in list. This currently only checks
3309 if (MRI->tracksLiveness())
3319 report("Live in register not found to be live out from predecessor.",
3321 errs() << TRI->getName(LiveInReg)
3322 << " not found to be live out from "
3328 for (auto CSInfo : MF->getCallSitesInfo())
3329 if (!CSInfo.first->isCall())
3332 // If there's debug-info, check that we don't have any duplicate value
3334 if (MF->getFunction().getSubprogram()) {
3350 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3352 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
3361 << " must be live through the block.\n";
3367 << " is not needed live through the block.\n";
3376 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
3380 if (MRI->reg_nodbg_empty(Reg))
3383 if (!LiveInts->hasInterval(Reg)) {
3384 report("Missing live interval for virtual register", MF);
3389 const LiveInterval &LI = LiveInts->getInterval(Reg);
3395 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
3396 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
3403 if (VNI->isUnused())
3406 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
3409 report("Value not live at VNInfo def and not marked unused", MF);
3416 report("Live segment at def has different VNInfo", MF);
3422 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
3430 if (VNI->isPHIDef()) {
3431 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
3439 // Non-PHI def.
3440 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
3452 if (!MOI->isReg() || !MOI->isDef())
3455 if (MOI->getReg() != Reg)
3458 if (!MOI->getReg().isPhysical() || !TRI->hasRegUnit(MOI->getReg(), Reg))
3462 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3465 if (MOI->isEarlyClobber())
3478 if (!VNI->def.isEarlyClobber()) {
3479 report("Early clobber def must be at an early-clobber slot", MBB);
3483 } else if (!VNI->def.isRegister()) {
3484 report("Non-PHI, non-early clobber def must be at a register slot", MBB);
3497 assert(VNI && "Live segment has no valno");
3499 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
3500 report("Foreign valno in live segment", MF);
3506 if (VNI->isUnused()) {
3507 report("Live segment valno is marked unused", MF);
3512 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
3514 report("Bad start of live segment, no basic block", MF);
3519 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
3520 if (S.start != MBBStartIdx && S.start != VNI->def) {
3521 report("Live segment must begin at MBB entry or valno def", MBB);
3527 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
3529 report("Bad end of live segment, no basic block", MF);
3535 // Checks for non-live-out segments.
3536 if (S.end != LiveInts->getMBBEndIdx(EndMBB)) {
3538 if (!Reg.isVirtual() && VNI->isPHIDef() && S.start == VNI->def &&
3539 S.end == VNI->def.getDeadSlot())
3542 // The live segment is ending inside EndMBB
3544 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
3546 report("Live segment doesn't end at a valid instruction", EndMBB);
3554 report("Live segment ends at B slot of an instruction", EndMBB);
3563 report("Live segment ending at dead slot spans instructions", EndMBB);
3569 // After tied operands are rewritten, a live segment can only end at an
3570 // early-clobber slot if it is being redefined by an early-clobber def.
3571 // TODO: Before tied operands are rewritten, a live segment can only end at
3572 // an early-clobber slot if the last use is tied to an early-clobber def.
3573 if (MF->getProperties().hasProperty(
3576 if (I + 1 == LR.end() || (I + 1)->start != S.end) {
3577 report("Live segment ending at early clobber slot must be "
3588 // A live segment can end with either a redefinition, a kill flag on a
3594 if (!MOI->isReg() || MOI->getReg() != Reg)
3596 unsigned Sub = MOI->getSubReg();
3598 Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) : LaneBitmask::getAll();
3599 if (MOI->isDef()) {
3603 // mask for subregister defs. Read-undef defs will be handled by
3607 if (MOI->isDead())
3612 if (MOI->readsReg())
3616 // Make sure that the corresponding machine operand for a "dead" live
3621 "Instruction ending live segment on dead slot has no dead flag",
3630 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3632 report("Instruction ending live segment doesn't read the register",
3642 // Now check all the basic blocks in this live segment.
3643 MachineFunction::const_iterator MFI = MBB->getIterator();
3644 // Is this live segment the beginning of a non-PHIDef VN?
3645 if (S.start == VNI->def && !VNI->isPHIDef()) {
3646 // Not live-in to any blocks.
3655 LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3660 assert(LiveInts->isLiveInToMBB(LR, &*MFI));
3662 if (!Reg.isVirtual() && MFI->isEHPad()) {
3669 // Is VNI a PHI-def in the current block?
3670 bool IsPHI = VNI->isPHIDef() &&
3671 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3673 // Check that VNI is live-out of all predecessors.
3674 for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3675 SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3676 // Predecessor of landing pad live-out on last call.
3677 if (MFI->isEHPad()) {
3680 PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3687 // All predecessors must have a live-out value. However for a phi
3694 report("Register not marked live out of predecessor", Pred);
3697 errs() << " live into " << printMBBReference(*MFI) << '@'
3698 << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3703 // Only PHI-defs can take different predecessor values.
3705 report("Different value live out of predecessor", Pred);
3707 errs() << "Valno #" << PVNI->id << " live out of "
3709 << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3710 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3735 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
3738 report("Lane masks of sub ranges overlap in live interval", MF);
3762 report("Multiple connected components in live interval", MF);
3768 errs() << ' ' << I->id;
3799 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3800 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3805 SPState.resize(MF->getNumBlockIDs());
3818 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3821 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3822 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3827 if ((int)MBB->getCallFrameSize() != -BBState.EntryValue) {
3831 errs() << "Call frame size on entry " << MBB->getCallFrameSize()
3833 << -BBState.EntryValue << '\n';
3841 if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
3844 BBState.ExitValue -= TII->getFrameTotalSize(I);
3849 int Size = TII->getFrameTotalSize(I);
3852 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3859 if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
3866 SPState[MBB->getNumber()] = BBState;
3870 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3872 (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3873 SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3876 << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3877 << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3885 for (const MachineBasicBlock *Succ : MBB->successors()) {
3887 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3888 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3891 << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3892 << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3899 if (!MBB->empty() && MBB->back().isReturn()) {