Lines Matching defs:MONum
252 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
260 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
278 void checkLiveness(const MachineOperand *MO, unsigned MONum);
279 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
283 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
577 unsigned MONum, LLT MOVRegType) {
580 errs() << "- operand " << MONum << ": ";
2379 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
2384 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
2387 if (MONum < NumDefs) {
2388 const MCOperandInfo &MCOI = MCID.operands()[MONum];
2390 report("Explicit definition must be a register", MO, MONum);
2392 report("Explicit definition marked as use", MO, MONum);
2394 report("Explicit definition marked as implicit", MO, MONum);
2395 } else if (MONum < MCID.getNumOperands()) {
2396 const MCOperandInfo &MCOI = MCID.operands()[MONum];
2399 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
2403 report("Explicit operand marked as def", MO, MONum);
2405 report("Explicit operand marked as implicit", MO, MONum);
2411 report("Expected a register operand.", MO, MONum);
2416 report("Expected a non-register operand.", MO, MONum);
2420 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
2423 report("Tied use must be a register", MO, MONum);
2425 report("Operand should be tied", MO, MONum);
2426 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
2427 report("Tied def doesn't match MCInstrDesc", MO, MONum);
2437 report("Explicit operand should not be tied", MO, MONum);
2441 report("Extra explicit operand on non-variadic instruction", MO, MONum);
2450 report("Register operand must be marked debug", MO, MONum);
2452 report("Register operand must not be marked debug", MO, MONum);
2459 checkLiveness(MO, MONum);
2463 report("Undef virtual register def operands require a subregister", MO, MONum);
2467 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
2470 report("Must be tied to a register", MO, MONum);
2472 report("Missing tie flags on tied operand", MO, MONum);
2473 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
2474 report("Inconsistent tie links", MO, MONum);
2475 if (MONum < MCID.getNumDefs()) {
2479 MO, MONum);
2482 report("Explicit def should be tied to implicit use", MO, MONum);
2497 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2499 report("Two-address instruction operands must be identical", MO, MONum);
2506 report("Illegal subregister index for physical register", MO, MONum);
2509 if (MONum < MCID.getNumOperands()) {
2511 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2513 report("Illegal physical register for instruction", MO, MONum);
2521 report("isRenamable set on reserved register", MO, MONum);
2538 report("Generic virtual register use cannot be undef", MO, MONum);
2550 MO, MONum);
2558 MONum);
2569 MO, MONum);
2577 MONum);
2587 MONum);
2595 MONum < MCID.getNumOperands() &&
2596 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2598 MONum);
2601 TII->getRegClass(MCID, MONum, TRI, *MF))
2612 report("Invalid subregister index for virtual register", MO, MONum);
2618 report("Invalid register class for subregister index", MO, MONum);
2624 if (MONum < MCID.getNumOperands()) {
2626 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2631 report("No largest legal super class exists.", MO, MONum);
2636 report("No matching super-reg register class.", MO, MONum);
2641 report("Illegal virtual register for instruction", MO, MONum);
2658 report("PHI operand is not in the CFG", MO, MONum);
2692 report("Instruction loads from dead spill slot", MO, MONum);
2696 report("Instruction stores to dead spill slot", MO, MONum);
2704 report("CFI instruction has invalid index", MO, MONum);
2713 unsigned MONum, SlotIndex UseIdx,
2723 report("No live segment at use", MO, MONum);
2729 report("Live range continues after kill flag", MO, MONum);
2739 unsigned MONum, SlotIndex DefIdx,
2757 report("Inconsistent valno->def", MO, MONum);
2766 report("No live segment at def", MO, MONum);
2784 report("Live range continues after dead def flag", MO, MONum);
2794 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2805 report("Live interval for subreg operand has no subranges", MO, MONum);
2807 report("Virtual register has no live interval", MO, MONum);
2823 report("Kill missing from LiveVariables", MO, MONum);
2832 MI->getOperand(MONum + 1).getMBB()).getPrevSlot();
2842 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
2848 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2858 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2865 report("No live subrange at use", MO, MONum);
2871 report("Not all lanes of PHI source live at use", MO, MONum);
2911 report("Using an undefined physical register", MO, MONum);
2913 report("Reading virtual register without a def", MO, MONum);
2920 report("Using a killed virtual register", MO, MONum);
2938 report("Multiple virtual register defs in SSA form", MO, MONum);
2946 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2955 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);