Lines Matching defs:UseMI

667 // Get the input data dependencies that must be ready before UseMI can issue.
668 // Return true if UseMI has any physreg operands.
669 static bool getDataDeps(const MachineInstr &UseMI,
673   if (UseMI.isDebugInstr())
677   for (const MachineOperand &MO : UseMI.operands()) {
697 static void getPHIDeps(const MachineInstr &UseMI,
704   assert(UseMI.isPHI() && UseMI.getNumOperands() % 2 && "Bad PHI");
705   for (unsigned i = 1; i != UseMI.getNumOperands(); i += 2) {
706     if (UseMI.getOperand(i + 1).getMBB() == Pred) {
707       Register Reg = UseMI.getOperand(i).getReg();
714 // Identify physreg dependencies for UseMI, and update the live regunit
716 static void updatePhysDepsDownwards(const MachineInstr *UseMI,
723   for (const MachineOperand &MO : UseMI->operands()) {
747   // Update RegUnits to reflect live registers after UseMI.
756          TRI->regunits(UseMI->getOperand(DefOp).getReg().asMCReg())) {
758       LRU.MI = UseMI;
795 updateDepth(MachineTraceMetrics::TraceBlockInfo &TBI, const MachineInstr &UseMI,
799   if (UseMI.isPHI())
800     getPHIDeps(UseMI, Deps, TBI.Pred, MTM.MRI);
801   else if (getDataDeps(UseMI, Deps, MTM.MRI))
802     updatePhysDepsDownwards(&UseMI, Deps, RegUnits, MTM.TRI);
817         .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
821   InstrCycles &MICycles = Cycles[&UseMI];
827     LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI);
829     LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI);
834 updateDepth(const MachineBasicBlock *MBB, const MachineInstr &UseMI,
836   updateDepth(BlockInfo[MBB->getNumber()], UseMI, RegUnits);
896     for (const auto &UseMI : *MBB) {
897       updateDepth(TBI, UseMI, RegUnits);
930         // We may not know the UseMI of this dependency, if it came from the
931         // live-in list. SchedModel can handle a NULL UseMI.
960 // Push the height of DefMI upwards if required to match UseMI.
962 static bool pushDepHeight(const DataDep &Dep, const MachineInstr &UseMI,
968     UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI,
1283                                               const MachineInstr &UseMI) const {
1284   if (DefMI.getParent() == UseMI.getParent())
1288   const TraceBlockInfo &TBI = TE.BlockInfo[UseMI.getParent()->getNumber()];