Lines Matching defs:DefOp

647   unsigned DefOp;
650   DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp)
651     : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
660     DefOp = DefI.getOperandNo();
754   for (unsigned DefOp : LiveDefOps) {
756          TRI->regunits(UseMI->getOperand(DefOp).getReg().asMCReg())) {
759       LRU.Op = DefOp;
817         .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp);
968     UseHeight += SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI,
984 /// Assuming that the virtual register defined by DefMI:DefOp was used by
988 addLiveIns(const MachineInstr *DefMI, unsigned DefOp,
991   Register Reg = DefMI->getOperand(DefOp).getReg();
1094             addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack);
1124           addLiveIns(Dep.DefMI, Dep.DefOp, Stack);
1195     DepCycle += TE.MTM.SchedModel.computeOperandLatency(Dep.DefMI, Dep.DefOp,