Lines Matching full:scheduling
81 cl::desc("Force top-down list scheduling"));
83 cl::desc("Force bottom-up list scheduling"));
93 cl::desc("Post reg-alloc list scheduling direction"),
99 "Force top-down post reg-alloc list scheduling"),
101 "Force bottom-up post reg-alloc list scheduling"),
103 "Force bidirectional post reg-alloc list scheduling")));
110 cl::desc("Verify machine instrs before and after machine scheduling"));
142 cl::desc("Stop scheduling after N instructions"), cl::init(~0U));
156 cl::desc("Enable register pressure scheduling."), cl::init(true));
205 // Machine Instruction Scheduling Pass and Registry
340 cl::desc("Enable the machine instruction scheduling pass."), cl::init(true),
345 cl::desc("Enable the post-ra machine instruction scheduling pass."),
404 /// Instantiate a ScheduleDAGInstrs for PostRA scheduling that will be owned by
419 /// Visit blocks in function order. Divide each block into scheduling regions
422 /// scheduling regions bottom-up.
424 /// This design avoids exposing scheduling boundaries to the DAG builder,
427 /// scheduling boundaries, for example to bundle the boundary instructions
431 /// design would be to split blocks at scheduling boundaries, but LLVM has a
456 MF->verify(this, "Before machine scheduling.");
475 MF->verify(this, "After machine scheduling.");
499 MF->verify(this, "Before post machine scheduling.");
515 MF->verify(this, "After post machine scheduling.");
519 /// Return true of the given instruction should not be included in a scheduling
522 /// MachineScheduler does not currently support scheduling across calls. To
525 /// operand. In PreRA scheduling, the stack pointer adjustment already prevents
526 /// scheduling across calls. In PostRA scheduling, we need the isCall to enforce
527 /// the boundary, but there would be no benefit to postRA scheduling across
536 /// A region of an MBB for scheduling.
539 /// RegionBegin is the first instruction in the scheduling region, and
540 /// RegionEnd is either MBB->end() or the scheduling boundary after the
541 /// last instruction in the scheduling region. These iterators cannot refer
542 /// to instructions outside of the identified scheduling region because
543 /// those may be reordered before scheduling this region.
588 // It's possible we found a scheduling region that only has debug
589 // instructions. Don't bother scheduling these.
618 // Break the block into scheduling regions [I, RegionEnd). RegionEnd
619 // points to the scheduling boundary at the bottom of the region. The DAG
639 // Notify the scheduler of the region, even if we may skip scheduling
643 // Skip empty scheduling regions (0 or 1 schedulable instructions).
650 LLVM_DEBUG(dbgs() << "********** MI Scheduling **********\n");
694 // ScheduleDAGMI - Basic machine instruction scheduling. This is
695 // independent of PreRA/PostRA scheduling and involves no extra book-keeping for
717 dbgs() << "*** Scheduling failed! ***\n";
754 dbgs() << "*** Scheduling failed! ***\n";
787 /// after crossing a scheduling boundary. [begin, end) includes all instructions
801 /// by the scheduling strategy to perform additional code motion.
831 /// Per-region scheduling driver, called back from
834 /// PostRA scheduling and potentially other custom schedulers.
888 // Notify the scheduling strategy before updating the DAG.
939 // Release all DAG roots for scheduling, not including EntrySU/ExitSU.
963 /// Update scheduler queues after scheduling an instruction.
965 // Release dependent instructions for scheduling.
1185 // ScheduleDAGMILive - Base class for MachineInstr scheduling with LiveIntervals
1232 /// crossing a scheduling boundary. [begin, end) includes all instructions in
1358 /// Update the PressureDiff array for liveness after scheduling this
1452 /// after setting up the current scheduling region. [RegionBegin, RegionEnd)
1453 /// only includes instructions that have DAG nodes, not scheduling boundaries.
1458 /// scheduling algorithm. However, if a scheduler further subclasses
1503 // Notify the scheduling strategy after updating the DAG.
1554 /// Compute the max cyclic critical path through the DAG. The scheduling DAG
1578 /// This could be relevant to PostRA scheduling, but is currently implemented
2038 // scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
2098 // edge, we cannot successfully contrain the copy without cyclic scheduling.
2149 "Disconnected LRG within the scheduling region.");
2235 /// If we are checking after scheduling a node, we should return true when
2335 /// available for scheduling until they are ready. However, a weaker in-order
2366 // For bottom-up scheduling add the cycles needed for the current operation.
2560 // scheduling, so may now be greater than ReadyCycle.
2683 // scheduling, clear the pipeline state before emitting.
2687 // Scheduling an instruction may have made pending instructions available.
2690 // checkHazard should prevent scheduling multiple instructions per cycle that
2754 // For top-down scheduling, this is the cycle in which we schedule this
2993 /// The "dependent" latency is updated incrementally during scheduling as the
3015 /// the critical path in the scheduling region.
3035 /// Set the CandPolicy given a scheduling zone given the current resources and
3061 // skip PostRA scheduling.
3277 /// Initialize the per-region scheduling policy.
3312 // Check -misched-topdown/bottomup can force or unforce scheduling direction.
3313 // e.g. -misched-bottomup=false allows scheduling in both directions.
3465 // towards scheduling this later. Make sure all register defs are to
3640 /// DAG building. To adjust for the current scheduling location we need to
3800 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
3829 /// Update the scheduler's state after scheduling a node. This is the same node
3931 /// Apply a set of heuristics to a new candidate for PostRA scheduling.
4125 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
4235 << "Scheduling " << *SU->getInstr());
4280 /// instruction order prior to scheduling. IsReverse implements greater-than.
4302 // When scheduling bottom-up, use greater-than as the queue priority.
4453 viewGraph(getDAGName(), "Scheduling-Units Graph for " + getDAGName());