Lines Matching defs:SSD

1083 static void computeScheduledInsts(const SwingSchedulerDAG *SSD,
1104     CycleInstrs = Schedule.reorderInstructions(SSD, CycleInstrs);
1553   bool detect(const SwingSchedulerDAG *SSD, SMSchedule &Schedule,
1560     computeScheduledInsts(SSD, Schedule, OrderedInsts, Stages);
2977 void SMSchedule::orderDependence(const SwingSchedulerDAG *SSD, SUnit *SU,
2998           if (unsigned NewReg = SSD->getInstrBaseReg(SU))
3034                  isLoopCarriedDefOfUse(SSD, (*I)->getInstr(), MO)) {
3091     orderDependence(SSD, UseSU, Insts);
3092     orderDependence(SSD, SU, Insts);
3093     orderDependence(SSD, DefSU, Insts);
3105 bool SMSchedule::isLoopCarried(const SwingSchedulerDAG *SSD,
3110   SUnit *DefSU = SSD->getSUnit(&Phi);
3117   SUnit *UseSU = SSD->getSUnit(MRI.getVRegDef(LoopVal));
3134 bool SMSchedule::isLoopCarriedDefOfUse(const SwingSchedulerDAG *SSD,
3144   if (!isLoopCarried(SSD, *Phi))
3169     SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {
3173   for (auto &SU : SSD->SUnits)
3196     SwingSchedulerDAG *SSD, TargetInstrInfo::PipelinerLoopInfo *PLI) {
3197   SmallSet<SUnit *, 8> DNP = computeUnpipelineableNodes(SSD, PLI);
3200   for (SUnit &SU : SSD->SUnits) {
3237 bool SMSchedule::isValidSchedule(SwingSchedulerDAG *SSD) {
3238   for (SUnit &SU : SSD->SUnits) {
3405 SMSchedule::reorderInstructions(const SwingSchedulerDAG *SSD,
3415       orderDependence(SSD, SU, NewOrderI);
3424 void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) {
3443   for (const SUnit &SU : SSD->SUnits)
3444     SSD->applyInstrChange(SU.getInstr(), *this);
3450     cycleInstrs = reorderInstructions(SSD, cycleInstrs);
3451     SSD->fixupRegisterOverlaps(cycleInstrs);