Lines Matching defs:InsInstrs

96   unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
104 SmallVectorImpl<MachineInstr *> &InsInstrs,
109 SmallVectorImpl<MachineInstr *> &InsInstrs,
114 SmallVectorImpl<MachineInstr *> &InsInstrs,
120 SmallVectorImpl<MachineInstr *> &InsInstrs,
200 /// \param InsInstrs is a vector of machine instructions
202 /// of defining machine instruction in \p InsInstrs
205 /// \returns Depth of last instruction in \InsInstrs ("NewRoot")
207 MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
215 for (auto *InstrPtr : InsInstrs) { // for each Use
228 MachineInstr *DefInstr = InsInstrs[II->second];
258 unsigned NewRootIdx = InsInstrs.size() - 1;
320 MachineInstr &MI, SmallVectorImpl<MachineInstr *> &InsInstrs,
323 assert(!InsInstrs.empty() && "Only support sequences that insert instrs.");
325 // NewRoot is the last instruction in the \p InsInstrs vector.
326 MachineInstr *NewRoot = InsInstrs.back();
327 for (unsigned i = 0; i < InsInstrs.size() - 1; i++)
328 NewRootLatency += TSchedModel.computeInstrLatency(InsInstrs[i]);
340 SmallVectorImpl<MachineInstr *> &InsInstrs,
345 // accurate compare of register pressure with DelInstrs or InsInstrs.
357 SmallVectorImpl<MachineInstr *> &InsInstrs,
363 getDepth(InsInstrs, InstrIdxForVirtReg, BlockTrace, *MBB);
390 getLatenciesForInstrSequences(*Root, InsInstrs, DelInstrs, BlockTrace);
392 NewRootLatency = TSchedModel.computeInstrLatency(InsInstrs.back());
430 SmallVectorImpl<MachineInstr *> &InsInstrs,
446 instr2instrSC(InsInstrs, InsInstrsSC);
470 /// Inserts InsInstrs and deletes DelInstrs. Incrementally updates instruction
475 /// \param InsInstrs new instructions to insert in \p MBB
485 SmallVectorImpl<MachineInstr *> &InsInstrs,
493 // better pattern InsInstrs or DelInstrs, so we don't want generate some
495 // entry creation here after InsInstrs is selected as better pattern.
496 // Otherwise the constant pool entry created for InsInstrs will not be deleted
497 // even if InsInstrs is not the better pattern.
498 TII->finalizeInsInstrs(MI, Pattern, InsInstrs);
500 for (auto *InstrPtr : InsInstrs)
515 for (auto *InstrPtr : InsInstrs)
531 SmallVector<MachineInstr *, 16> InsInstrs;
534 TII->genAlternativeCodeSequence(Root, P, InsInstrs, DelInstrs,
539 if (InsInstrs.empty() || !TSchedModel.hasInstrSchedModelOrItineraries())
544 Root, InsInstrs, DelInstrs, TraceEnsemble->getTrace(MBB));
616 SmallVector<MachineInstr *, 16> InsInstrs;
619 TII->genAlternativeCodeSequence(MI, P, InsInstrs, DelInstrs,
624 if (InsInstrs.empty())
634 for (auto const *InstrPtr : InsInstrs)
653 if (reduceRegisterPressure(MI, MBB, InsInstrs, DelInstrs, P)) {
654 // Replace DelInstrs with InsInstrs.
655 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
668 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
673 } else if (OptForSize && InsInstrs.size() < DelInstrs.size()) {
675 << InsInstrs.size() << " < "
677 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
690 if (improvesCriticalPathLen(MBB, &MI, BlockTrace, InsInstrs, DelInstrs,
693 preservesResourceLen(MBB, BlockTrace, InsInstrs, DelInstrs)) {
700 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
710 for (auto *InstrPtr : InsInstrs)