Lines Matching defs:DefInstr

154   MachineInstr *DefInstr = nullptr;
157     DefInstr = MRI->getUniqueVRegDef(MO.getReg());
158   return DefInstr;
228         MachineInstr *DefInstr = InsInstrs[II->second];
229         assert(DefInstr &&
233             DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr);
236         LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,
239         MachineInstr *DefInstr = getOperandDef(MO);
240         if (DefInstr && (TII->getMachineCombinerTraceStrategy() !=
242                          DefInstr->getParent() == &MBB)) {
243           DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth;
244           if (!isTransientMI(DefInstr))
246                 DefInstr,
247                 DefInstr->findRegisterDefOperandIdx(MO.getReg(),