Lines Matching +full:keep +full:- +full:a +full:- +full:live
1 //===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
16 // This class computes live variables using a sparse implementation based on
17 // the machine code SSA form. This class computes live variable information for
18 // each virtual and _register allocatable_ physical register in a function. It
19 // uses the dominance properties of SSA form to efficiently compute live
21 // live within a single basic block (allowing it to do a single local analysis
22 // to resolve physical register lifetimes in each basic block). If a physical
26 //===----------------------------------------------------------------------===//
37 #include "llvm/Config/llvm-config.h"
55 OS << "Live variables in machine function: " << MF.getName() << '\n';
63 "Live Variable Analysis", false, false)
66 "Live Variable Analysis", false, false)
90 if (MI->getParent() == MBB)
113 /// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
115 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!");
123 unsigned BBNum = MBB->getNumber();
128 if (VRInfo.Kills[i]->getParent() == MBB) {
136 return; // We already know the block is live
141 assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
142 WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
159 assert(MRI->getVRegDef(Reg) && "Register use before def!");
161 unsigned BBNum = MBB->getNumber();
165 // Check to see if this basic block is already a kill block.
166 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
168 // live range by updating the kill instruction.
175 assert(Kill->getParent() != MBB && "entry should be at end!");
180 // ,------.
189 // `------'
191 // where there is a use in a PHI node that's a predecessor to the defining
194 if (MBB == MRI->getVRegDef(Reg)->getParent())
197 // Add a new kill entry for this basic block. If this virtual register is
199 // least one of the successor blocks, it's not a kill.
203 // Update all dominating blocks to mark them as "known live".
204 for (MachineBasicBlock *Pred : MBB->predecessors())
205 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred);
216 /// FindLastPartialDef - Return the last partial def of the specified register.
217 /// Also returns the sub-registers that're defined by the instruction.
224 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
240 for (MachineOperand &MO : LastDef->all_defs()) {
244 if (TRI->isSubRegister(Reg, DefReg)) {
245 for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg))
252 /// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
253 /// implicit defs to a machine instruction if there was an earlier def of its
254 /// super-register.
257 // If there was a previous use or a "full" def all is well.
259 // Otherwise, the last sub-register def implicitly defines this register.
262 // AL = ... implicit-def EAX, implicit killed AH
266 // All of the sub-registers must have been defined before the use of Reg!
269 // If LastPartialDef is NULL, it must be using a livein register.
271 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
275 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
282 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
286 for (MCPhysReg SS : TRI->subregs(SubReg))
291 !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
293 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
297 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
301 /// FindLastRefOrPartRef - Return the last reference or partial reference of
312 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
315 // There was a def of this sub-register in between. This is a partial
316 // def, keep track of the last one.
354 // dead AX = implicit-def AL
360 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
363 // There was a def of this sub-register in between. This is a partial
364 // def, keep track of the last one.
373 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
385 // sub-registers which are used.
386 // dead EAX = op implicit-def AL
388 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
389 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
395 PhysRegDef[Reg]->findRegisterDefOperand(SubReg, /*TRI=*/nullptr);
398 assert(!MO->isDead());
402 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
406 LastSubRef->addRegisterKilled(SubReg, TRI, true);
408 LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
409 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
412 for (MCPhysReg SS : TRI->subregs(SubReg))
418 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
422 LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false);
423 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
426 LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
428 // If we are adding a subreg def and the superreg def is marked early
430 MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr);
432 MO->setIsEarlyClobber();
436 LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
441 // Call HandlePhysRegKill() for all live registers clobbered by Mask.
448 // Skip mask-preserved regs.
451 // Kill the largest clobbered super-register.
454 for (MCPhysReg SR : TRI->superregs(Reg))
465 SmallSet<unsigned, 32> Live;
467 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
468 Live.insert(SubReg);
470 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
471 // If a register isn't itself defined, but all parts that make up of it
477 if (Live.count(SubReg))
480 for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
481 Live.insert(SS);
489 // Only some of the sub-registers are used.
490 for (MCPhysReg SubReg : TRI->subregs(Reg)) {
491 if (!Live.count(SubReg))
492 // Skip if this sub-register isn't defined.
505 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
519 // Unless it is a PHI node. In this case, ONLY process the DEF, not any
538 if (!(MOReg.isPhysical() && MRI->isReserved(MOReg)))
546 if (MOReg.isPhysical() && !MRI->isReserved(MOReg))
557 else if (!MRI->isReserved(MOReg))
569 else if (!MRI->isReserved(MOReg))
576 // Mark live-in registers as live-in.
578 for (const auto &LI : MBB->liveins()) {
580 "Cannot have a live-in virtual register!");
599 if (!PHIVarInfo[MBB->getNumber()].empty()) {
600 SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
604 MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(),
608 // MachineCSE may CSE instructions which write to non-allocatable physical
611 for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
612 if (SuccMBB->isEHPad())
614 for (const auto &LI : SuccMBB->liveins()) {
615 if (!TRI->isInAllocatableClass(LI.PhysReg))
616 // Ignore other live-ins, e.g. those that are live into landing pads.
631 TRI = MF->getSubtarget().getRegisterInfo();
633 const unsigned NumRegs = TRI->getNumSupportedRegs(mf);
636 PHIVarInfo.resize(MF->getNumBlockIDs());
640 // dependencies. Until then, we can't change much in -O0.
641 if (!MRI->isSSA())
642 report_fatal_error("regalloc=... not currently supported with -O0");
646 // Calculate live variable information in depth first order on the CFG of the
647 // function. This guarantees that we will see the definition of a virtual
649 // nodes, which are treated as a special case).
650 MachineBasicBlock *Entry = &MF->front();
665 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
666 VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
668 VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
672 // function. If so, it is due to a bug in the instruction selector or some
691 MachineInstr &DefMI = *MRI->getUniqueVRegDef(Reg);
694 // Initialize a worklist of BBs that Reg is live-to-end of. (Here
695 // "live-to-end" means Reg is live at the end of a block even if it is only
696 // live because of phi uses in a successor. This is different from isLiveOut()
701 for (auto &UseMO : MRI->use_nodbg_operands(Reg)) {
710 // If Reg is used in a phi then it is live-to-end of the corresponding
715 // A non-phi use in the same BB as the single def must come after the def.
717 // Otherwise Reg must be live-to-end of all predecessors.
745 // live-through, find the last instruction that uses Reg. Ignore phi nodes
750 MachineBasicBlock &UseBB = *MF->getBlockNumbered(UseBBNum);
768 /// replaceKillInstruction - Update register kill info by replacing a kill
769 /// instruction with a new one.
776 /// removeVirtualRegistersKilled - Remove all killed info for the specified
792 /// analyzePHINodes - Gather information about the PHI nodes in here. In
793 /// particular, we want to map the variable information of a virtual register
794 /// which is used in a PHI node. We map that to the BB the vreg is coming from.
803 PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
812 // Reg is live-through.
816 // Registers defined in MBB cannot be live in.
818 if (Def && Def->getParent() == &MBB)
830 Kills.insert(MI->getParent());
833 // the value is either live in the block, or if it is killed in the block.
836 unsigned SuccIdx = SuccMBB->getNumber();
839 // Or is it live because there is a use in a successor that kills it?
847 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
848 /// variables that are live out of DomBB will be marked as passing live through
853 const unsigned NumNew = BB->getNumber();
857 MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
858 for (; BBI != BBE && BBI->isPHI(); ++BBI) {
860 Defs.insert(BBI->getOperand(0).getReg());
862 // All registers used by PHI nodes in SuccBB must be live through BB.
863 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
864 if (BBI->getOperand(i+1).getMBB() == BB)
865 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
870 for (const MachineOperand &Op : BBI->operands()) {
880 // Update info for all live variables
881 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
884 // If the Defs is defined in the successor it can't be live in BB.
888 // If the register is either killed in or live through SuccBB it's also live
891 if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
896 /// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
897 /// variables that are live out of DomBB will be marked as passing live through
904 const unsigned NumNew = BB->getNumber();
906 SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()];
912 // All registers used by PHI nodes in SuccBB must be live through BB.
913 for (MachineBasicBlock::iterator BBI = SuccBB->begin(),
914 BBE = SuccBB->end();
915 BBI != BBE && BBI->isPHI(); ++BBI) {
916 for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
917 if (BBI->getOperand(i + 1).getMBB() == BB &&
918 BBI->getOperand(i).readsReg())
919 getVarInfo(BBI->getOperand(i).getReg())