Lines Matching +full:keep +full:- +full:a +full:- +full:live
1 //===- LiveIntervals.cpp - Live Interval Analysis -------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 /// basic blocks of the function in DFS order and computes live intervals for
14 //===----------------------------------------------------------------------===//
39 #include "llvm/Config/llvm-config.h"
72 OS << "Live intervals for machine function: " << MF.getName() << ":\n";
80 "Live Interval Analysis", false, false)
84 "Live Interval Analysis", false, false)
96 "precompute-phys-liveness", cl::Hidden,
97 cl::desc("Eagerly compute live intervals for all physreg units."));
105 "use-segment-set-for-physregs", cl::Hidden, cl::init(true),
107 "Use segment set for the computation of the live ranges of physregs."));
129 // Free the live intervals themselves.
147 MRI = &MF->getRegInfo();
148 TRI = MF->getSubtarget().getRegisterInfo();
149 TII = MF->getSubtarget().getInstrInfo();
155 VirtRegIntervals.resize(MRI->getNumVirtRegs());
162 // For stress testing, precompute live ranges of all physical register
164 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
178 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
194 MF->print(OS, Indexes);
212 /// Compute the live interval of a virtual register, based on defs and uses.
216 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
217 LICalc->calculate(LI, MRI->shouldTrackSubRegLiveness(LI.reg()));
222 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
224 if (MRI->reg_nodbg_empty(Reg))
236 RegMaskBlocks.resize(MF->getNumBlockIDs());
245 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));
253 if (auto *Mask = TRI->getCustomEHPadPreservedMask(*MBB.getParent())) {
254 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));
262 RegMaskSlots.push_back(Indexes->getInstructionIndex(MI).getRegSlot());
269 // half-open.
273 Indexes->getInstructionIndex(MBB.back()).getRegSlot());
278 RMB.second = RegMaskSlots.size() - RMB.first;
282 //===----------------------------------------------------------------------===//
284 //===----------------------------------------------------------------------===//
293 /// Compute the live range of a register unit, based on the uses and defs of
295 /// phi-defs from ABI blocks.
298 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
300 // The physregs aliasing Unit are the roots and their super-registers.
302 // may share super-registers. That's OK because createDeadDefs() is
303 // idempotent. It is very rare for a register unit to have multiple roots, so
304 // uniquing super-registers is probably not worthwhile.
308 for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {
309 if (!MRI->reg_empty(Reg))
310 LICalc->createDeadDefs(LR, Reg);
311 // A register unit is considered reserved if all its roots and all their
313 if (!MRI->isReserved(Reg))
318 assert(IsReserved == MRI->isReservedRegUnit(Unit) &&
325 for (MCPhysReg Reg : TRI->superregs_inclusive(*Root)) {
326 if (!MRI->reg_empty(Reg))
327 LICalc->extendToUses(LR, Reg);
337 /// Precompute the live ranges of any register units that are live-in to an ABI
338 /// block somewhere. Register values can appear without a corresponding def when
339 /// entering the entry block or a landing pad.
341 RegUnitRanges.resize(TRI->getNumRegUnits());
342 LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
344 // Keep track of the live range sets allocated.
347 // Check all basic blocks for live-ins.
350 if ((&MBB != &MF->front() && !MBB.isEHPad()) || MBB.livein_empty())
353 // Create phi-defs at Begin for all live-in registers.
354 SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
357 for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
360 // Use segment set to speed-up initial computation of the live range.
364 VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
366 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id);
381 if (VNI->isUnused())
383 SlotIndex Def = VNI->def;
391 // Keep track of the PHIs that are in use.
393 // Blocks that have already been added to WorkList as live-out.
397 -> const LiveRange& {
417 const MachineBasicBlock *MBB = Indexes->getMBBFromIndex(Idx.getPrevSlot());
418 SlotIndex BlockStart = Indexes->getMBBStartIdx(MBB);
420 // Extend the live range for VNI to be live at Idx.
424 // Is this a PHIDef we haven't seen before?
425 if (!VNI->isPHIDef() || VNI->def != BlockStart ||
428 // The PHI is live, make sure the predecessors are live-out.
429 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
432 SlotIndex Stop = Indexes->getMBBEndIdx(Pred);
433 // A predecessor is not required to have a live-out value for a PHI.
440 // VNI is live-in to MBB.
441 LLVM_DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
444 // Make sure VNI is live-out from the predecessors.
445 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
448 SlotIndex Stop = Indexes->getMBBEndIdx(Pred);
456 // by <undef>s for this live range.
472 assert(li->reg().isVirtual() && "Can only shrink virtual registers");
474 // Shrink subregister live ranges.
476 for (LiveInterval::SubRange &S : li->subranges()) {
477 shrinkToUses(S, li->reg());
482 li->removeEmptySubRanges();
487 // Visit all instructions reading li->reg().
488 Register Reg = li->reg();
489 for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
493 LiveQueryResult LRQ = li->Query(Idx);
497 // no live value. It is likely caused by a target getting <undef> flags
501 << "Warning: Instr claims to read non-existent value in "
505 // Special case: An early-clobber tied operand reads and writes the
508 Idx = DefVNI->def;
513 // Create new live ranges with only minimal live segments per def.
515 createSegmentsForValues(NewLR, li->vnis());
519 li->segments.swap(NewLR.segments);
532 if (VNI->isUnused())
534 SlotIndex Def = VNI->def;
538 // Is the register live before? Otherwise we may have to add a read-undef
541 if (MRI->shouldTrackSubRegLiveness(VReg)) {
542 if ((I == LI.begin() || std::prev(I)->end < Def) && !VNI->isPHIDef()) {
544 MI->setRegisterDefReadUndef(VReg);
548 if (I->end != Def.getDeadSlot())
550 if (VNI->isPHIDef()) {
551 // This is a dead PHI. Remove it.
552 VNI->markUnused();
556 // This is a dead def. Make sure the instruction knows.
558 assert(MI && "No instruction defining live value");
559 MI->addRegisterDead(LI.reg(), TRI);
561 if (dead && MI->allDefsAreDead()) {
563 dead->push_back(MI);
579 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
583 // Maybe the operand is for a subregister we don't care about.
586 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
604 // Special case: An early-clobber tied operand reads and writes the
607 Idx = DefVNI->def;
612 // Create a new live ranges with only minimal live segments per def.
622 if (VNI->isUnused())
624 const LiveRange::Segment *Segment = SR.getSegmentContaining(VNI->def);
626 if (Segment->end != VNI->def.getDeadSlot())
628 if (VNI->isPHIDef()) {
629 // This is a dead PHI. Remove it.
630 LLVM_DEBUG(dbgs() << "Dead PHI at " << VNI->def
632 VNI->markUnused();
644 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
646 LICalc->extend(LR, Idx, /*PhysReg=*/0, Undefs);
656 MachineBasicBlock *KillMBB = Indexes->getMBBFromIndex(Kill);
657 SlotIndex MBBEnd = Indexes->getMBBEndIdx(KillMBB);
659 // If VNI isn't live out from KillMBB, the value is trivially pruned.
662 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
666 // VNI is live out of KillMBB.
668 if (EndPoints) EndPoints->push_back(MBBEnd);
670 // Find all blocks that are reachable from KillMBB without leaving VNI's live
671 // range. It is possible that KillMBB itself is reachable, so start a DFS
675 for (MachineBasicBlock *Succ : KillMBB->successors()) {
681 // Check if VNI is live in to MBB.
683 std::tie(MBBStart, MBBEnd) = Indexes->getMBBRange(MBB);
694 if (EndPoints) EndPoints->push_back(LRQ.endPoint());
699 // VNI is live through MBB.
701 if (EndPoints) EndPoints->push_back(MBBEnd);
707 //===----------------------------------------------------------------------===//
712 // Keep track of regunit ranges.
715 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
717 if (MRI->reg_nodbg_empty(Reg))
724 Register PhysReg = VRM->getPhys(Reg);
729 // the virtual register live range, cancelling any kills.
731 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
735 RU.push_back(std::make_pair(&RURange, RURange.find(LI.begin()->end)));
737 // Every instruction that kills Reg corresponds to a segment range end
741 // A block index indicates an MBB edge.
742 if (RI->end.isBlock())
744 MachineInstr *MI = getInstructionFromIndex(RI->end);
748 // Check if any of the regunits are live beyond the end of RI. That could
749 // happen when a physreg is defined as a copy of a virtreg:
752 // FOO %5 <--- MI, cancel kill because %eax is live.
761 I = RURange.advanceTo(I, RI->end);
762 if (I == RURange.end() || I->start >= RI->end)
768 if (MRI->subRegLivenessEnabled()) {
769 // When reading a partial undefined value we must not add a kill flag.
782 // Compute a mask of lanes that are defined.
786 if (Segment.start >= RI->end)
788 if (Segment.end == RI->end) {
797 for (const MachineOperand &MO : MI->operands()) {
803 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg)
804 : MRI->getMaxLaneMaskForVReg(Reg);
814 // If an instruction writes to a subregister, a new segment starts in
816 // adding kill-flags is not correct here after registers have been
821 if (N != LI.end() && N->start == RI->end)
826 MI->addRegisterKilled(Reg, nullptr);
829 MI->clearRegisterKills(Reg, nullptr);
838 // A local live range must be fully contained inside the block, meaning it is
840 // live in or out of any block.
842 // It is technically possible to have a PHI-defined live range identical to a
855 MachineBasicBlock *MBB1 = Indexes->getMBBFromIndex(Start);
856 MachineBasicBlock *MBB2 = Indexes->getMBBFromIndex(Stop);
863 if (PHI->isUnused() || !PHI->isPHIDef())
865 const MachineBasicBlock *PHIMBB = getMBBFromIndex(PHI->def);
867 if (PHIMBB->pred_size() > 100)
869 for (const MachineBasicBlock *Pred : PHIMBB->predecessors())
870 if (VNI == LI.getVNInfoBefore(Indexes->getMBBEndIdx(Pred)))
885 return (isDef + isUse) * MBFI->getBlockFreqRelativeToEntryBlock(MBB);
901 //===----------------------------------------------------------------------===//
903 //===----------------------------------------------------------------------===//
904 /// Check whether use of reg in MI is live-through. Live-through means that
906 /// use is a deopt value in statepoint instruction.
908 if (MI->getOpcode() != TargetOpcode::STATEPOINT)
915 const MachineOperand &MO = MI->getOperand(Idx);
928 // Use a smaller arrays for local live ranges.
932 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
933 Bits = getRegMaskBitsInBlock(MBB->getNumber());
940 // Start with a binary search of RegMaskSlots to find a starting point.
941 ArrayRef<SlotIndex>::iterator SlotI = llvm::lower_bound(Slots, LiveI->start);
954 UsableRegs.resize(TRI->getNumRegs(), true);
961 assert(*SlotI >= LiveI->start);
963 while (*SlotI < LiveI->end) {
965 unionBitMask(SlotI - Slots.begin());
969 // If segment ends with live-through use we need to collect its regmask.
970 if (*SlotI == LiveI->end)
973 unionBitMask(SlotI++ - Slots.begin());
975 // Special advance implementation to not miss next LiveI->end.
978 while (LiveI->end < *SlotI)
981 while (*SlotI < LiveI->start)
987 //===----------------------------------------------------------------------===//
989 //===----------------------------------------------------------------------===//
991 /// Toolkit used by handleMove to trim or extend live intervals.
1009 // FIXME: UpdateFlags is a workaround that creates live intervals for all
1012 // flags, and postRA passes will use a live register utility instead.
1019 /// Update all live ranges touched by MI, assuming a move from OldIdx to
1022 LLVM_DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": "
1025 for (MachineOperand &MO : MI->operands()) {
1054 // If main range has a hole and we are moving a subrange use across
1056 // gets the LiveRange and not the whole LiveInterval. As a result
1057 // we may end up with a main range not covering all subranges.
1076 // For physregs, only update the regunits that actually have a
1077 // precomputed live range.
1087 /// Update a single live range, assuming an instruction has been moved from
1107 LLVM_DEBUG(dbgs() << " -->\t" << LR << '\n');
1118 // No value live before or after OldIdx? Nothing to do.
1119 if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1123 // Do we have a value live-in to OldIdx?
1124 if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1125 // If the live-in value already extends to NewIdx, there is nothing to do.
1126 if (SlotIndex::isEarlierEqualInstr(NewIdx, OldIdxIn->end))
1129 // Kill flags shouldn't be used while live intervals exist, they will be
1131 if (MachineInstr *KillMI = LIS.getInstructionFromIndex(OldIdxIn->end))
1136 // Is there a def before NewIdx which is not OldIdx?
1138 if (Next != E && !SlotIndex::isSameInstr(OldIdx, Next->start) &&
1139 SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1140 // If we are here then OldIdx was just a use but not a def. We only have
1146 !SlotIndex::isEarlierInstr(NewIdxIn->start, NewIdx)) {
1148 Prev->end = NewIdx.getRegSlot();
1151 OldIdxIn->end = Next->start;
1155 // Adjust OldIdxIn->end to reach NewIdx. This may temporarily make LR
1157 bool isKill = SlotIndex::isSameInstr(OldIdx, OldIdxIn->end);
1158 OldIdxIn->end = NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber());
1159 // If this was not a kill, then there was no def and we're done.
1163 // Did we have a Def at OldIdx?
1165 if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1171 // If we are here then there is a Definition at OldIdx. OldIdxOut points
1173 assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1175 VNInfo *OldIdxVNI = OldIdxOut->valno;
1176 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1180 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1181 if (SlotIndex::isEarlierInstr(NewIdxDef, OldIdxOut->end)) {
1182 OldIdxVNI->def = NewIdxDef;
1183 OldIdxOut->start = OldIdxVNI->def;
1187 // If we are here then we have a Definition at OldIdx which ends before
1193 bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1195 SlotIndex::isEarlierInstr(OldIdxOut->end, NewIdxDef)) {
1196 // OldIdx is not a dead def, and NewIdxDef is inside a new interval.
1199 !SlotIndex::isEarlierInstr(std::prev(OldIdxOut)->end,
1200 OldIdxOut->start)) {
1205 IPrev->end = OldIdxOut->end;
1207 // The value is live in to OldIdx
1211 // reordering, there is always a successor to OldIdxOut in the same BB
1212 // We don't need INext->valno anymore and will reuse for the new segment
1215 INext->start = OldIdxOut->end;
1216 INext->valno->def = INext->start;
1218 // If NewIdx is behind the last segment, extend that and append a new one.
1222 // |- ?/OldIdxOut -| |- X0 -| ... |- Xn -| end
1223 // => |- X0/OldIdxOut -| ... |- Xn -| |- undef/NewS -| end
1225 // The last segment is undefined now, reuse it for a dead def.
1229 DefVNI->def = NewIdxDef;
1232 Prev->end = NewIdxDef;
1236 // |- ?/OldIdxOut -| |- X0 -| ... |- Xn/AfterNewIdx -| |- Next -|
1237 // => |- X0/OldIdxOut -| ... |- Xn -| |- Xn/AfterNewIdx -| |- Next -|
1241 if (SlotIndex::isEarlierInstr(Prev->start, NewIdxDef)) {
1242 // Case 1: NewIdx is inside a liverange. Split this liverange at
1245 *NewSegment = LiveRange::Segment(NewIdxDef, Prev->end, Prev->valno);
1246 Prev->valno->def = NewIdxDef;
1248 *Prev = LiveRange::Segment(Prev->start, NewIdxDef, DefVNI);
1249 DefVNI->def = Prev->start;
1251 // Case 2: NewIdx is in a lifetime hole. Keep AfterNewIdx as is and
1252 // turn Prev into a segment from NewIdx to AfterNewIdx->start.
1253 *Prev = LiveRange::Segment(NewIdxDef, AfterNewIdx->start, DefVNI);
1254 DefVNI->def = NewIdxDef;
1255 assert(DefVNI != AfterNewIdx->valno);
1262 SlotIndex::isSameInstr(AfterNewIdx->start, NewIdxDef)) {
1265 assert(AfterNewIdx->valno != OldIdxVNI && "Multiple defs of value?");
1268 // There was no existing def at NewIdx. We need to create a dead def
1270 // a new segment at the place where we want to construct the dead def.
1271 // |- OldIdxOut -| |- X0 -| ... |- Xn -| |- AfterNewIdx -|
1272 // => |- X0/OldIdxOut -| ... |- Xn -| |- undef/NewS. -| |- AfterNewIdx -|
1278 NewSegmentVNI->def = NewIdxDef;
1291 // No value live before or after OldIdx? Nothing to do.
1292 if (OldIdxIn == E || SlotIndex::isEarlierInstr(OldIdx, OldIdxIn->start))
1296 // Do we have a value live-in to OldIdx?
1297 if (SlotIndex::isEarlierInstr(OldIdxIn->start, OldIdx)) {
1298 // If the live-in value isn't killed here, then we have no Def at
1299 // OldIdx, moreover the value must be live at NewIdx so there is nothing
1301 bool isKill = SlotIndex::isSameInstr(OldIdx, OldIdxIn->end);
1305 // At this point we have to move OldIdxIn->end back to the nearest
1306 // previous use or (dead-)def but no further than NewIdx.
1308 = std::max(OldIdxIn->start.getDeadSlot(),
1309 NewIdx.getRegSlot(OldIdxIn->end.isEarlyClobber()));
1310 OldIdxIn->end = findLastUseBefore(DefBeforeOldIdx, Reg, LaneMask);
1312 // Did we have a Def at OldIdx? If not we are done now.
1314 if (OldIdxOut == E || !SlotIndex::isSameInstr(OldIdx, OldIdxOut->start))
1321 // If we are here then there is a Definition at OldIdx. OldIdxOut points
1323 assert(OldIdxOut != E && SlotIndex::isSameInstr(OldIdx, OldIdxOut->start) &&
1325 VNInfo *OldIdxVNI = OldIdxOut->valno;
1326 assert(OldIdxVNI->def == OldIdxOut->start && "Inconsistent def");
1327 bool OldIdxDefIsDead = OldIdxOut->end.isDead();
1330 SlotIndex NewIdxDef = NewIdx.getRegSlot(OldIdxOut->start.isEarlyClobber());
1332 if (SlotIndex::isSameInstr(NewIdxOut->start, NewIdx)) {
1333 assert(NewIdxOut->valno != OldIdxVNI &&
1335 // If OldIdx was a dead def remove it.
1339 OldIdxVNI->def = NewIdxDef;
1340 OldIdxOut->start = NewIdxDef;
1341 LR.removeValNo(NewIdxOut->valno);
1347 // Previously nothing was live after NewIdx, so all we have to do now is
1352 SlotIndex::isEarlierInstr(NewIdxDef, OldIdxIn->start)) {
1353 // OldIdx is not a dead def and NewIdx is before predecessor start.
1357 OldIdxVNI = OldIdxIn->valno;
1359 SlotIndex NewDefEndPoint = std::next(NewIdxIn)->end;
1362 SlotIndex::isEarlierInstr(NewIdx, Prev->end)) {
1363 // If the segment before OldIdx read a value defined earlier than
1369 NewDefEndPoint = std::min(OldIdxIn->start,
1370 std::next(NewIdxOut)->start);
1374 OldIdxOut->valno->def = OldIdxIn->start;
1375 *OldIdxOut = LiveRange::Segment(OldIdxIn->start, OldIdxOut->end,
1376 OldIdxOut->valno);
1379 // |- X0/NewIdxIn -| ... |- Xn-1 -||- Xn/OldIdxIn -||- OldIdxOut -|
1380 // => |- undef/NexIdxIn -| |- X0 -| ... |- Xn-1 -| |- Xn/OldIdxOut -|
1386 if (SlotIndex::isEarlierInstr(Next->start, NewIdx)) {
1388 *NewSegment = LiveRange::Segment(Next->start, SplitPos,
1389 Next->valno);
1392 Next->valno->def = SplitPos;
1394 // There is a gap between NewSegment and its predecessor
1395 // Value becomes live in.
1396 *NewSegment = LiveRange::Segment(SplitPos, Next->start, OldIdxVNI);
1397 NewSegment->valno->def = SplitPos;
1400 // Leave the end point of a live def.
1401 OldIdxOut->start = NewIdxDef;
1402 OldIdxVNI->def = NewIdxDef;
1403 if (OldIdxIn != E && SlotIndex::isEarlierInstr(NewIdx, OldIdxIn->end))
1404 OldIdxIn->end = NewIdxDef;
1407 && SlotIndex::isEarlierInstr(NewIdxOut->start, NewIdx)
1408 && SlotIndex::isEarlierInstr(NewIdx, NewIdxOut->end)) {
1409 // OldIdxVNI is a dead def that has been moved into the middle of
1410 // another value in LR. That can happen when LR is a whole register,
1411 // but the dead def is a write to a subreg that is dead at NewIdx.
1415 // |- X0/NewIdxOut -| ... |- Xn-1 -| |- Xn/OldIdxOut -| |- next - |
1416 // => |- X0/NewIdxOut -| |- X0 -| ... |- Xn-1 -| |- next -|
1422 NewIdxOut->start, NewIdxDef.getRegSlot(), NewIdxOut->valno);
1424 NewIdxDef.getRegSlot(), (NewIdxOut + 1)->end, OldIdxVNI);
1425 OldIdxVNI->def = NewIdxDef;
1428 Idx->valno = OldIdxVNI;
1430 // Kill/dead flags shouldn't be used while live intervals exist; they
1434 if (MO->isReg() && !MO->isUse())
1435 MO->setIsDead(false);
1437 // OldIdxVNI is a dead def. It may have been moved across other values
1440 // |- X0/NewIdxOut -| ... |- Xn-1 -| |- Xn/OldIdxOut -| |- next - |
1441 // => |- undef/NewIdxOut -| |- X0 -| ... |- Xn-1 -| |- next -|
1443 // OldIdxVNI can be reused now to build a new dead def segment.
1448 NewSegmentVNI->def = NewIdxDef;
1481 SlotIndex InstSlot = LIS.getSlotIndexes()->getInstructionIndex(MI);
1488 // This is a regunit interval, so scanning the use list could be very
1492 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(Before);
1495 // point to the next instruction after OldIdx, or MBB->end().
1496 MachineBasicBlock::iterator MII = MBB->end();
1497 if (MachineInstr *MI = Indexes->getInstructionFromIndex(
1498 Indexes->getNextNonNullIndex(OldIdx)))
1499 if (MI->getParent() == MBB)
1502 MachineBasicBlock::iterator Begin = MBB->begin();
1504 if ((--MII)->isDebugOrPseudoInstr())
1506 SlotIndex Idx = Indexes->getInstructionIndex(*MII);
1514 if (MO->isReg() && !MO->isUndef() && MO->getReg().isPhysical() &&
1515 TRI.hasRegUnit(MO->getReg(), Reg))
1524 // It is fine to move a bundle as a whole, but not an individual instruction
1528 SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
1529 Indexes->removeMachineInstrFromMaps(MI);
1530 SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
1542 "Bundle start is not a bundle");
1544 const SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(BundleStart);
1550 if (!Indexes->hasIndex(*I))
1552 SlotIndex OldIndex = Indexes->getInstructionIndex(*I, true);
1554 Indexes->removeMachineInstrFromMaps(*I, true);
1584 if (LII != LR.end() && LII->start < EndIdx) {
1585 lastUseIdx = LII->end;
1587 // We may not have a liverange at all if this is a subregister untouched
1590 --LII;
1594 --I;
1600 bool isStartValid = getInstructionFromIndex(LII->start);
1601 bool isEndValid = getInstructionFromIndex(LII->end);
1603 // FIXME: This doesn't currently handle early-clobber or multiple removed
1610 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
1616 if (LII->end.isDead()) {
1619 --LII;
1621 LII->start = instrIdx.getRegSlot();
1622 LII->valno->def = instrIdx.getRegSlot();
1636 } else if (LII->start != instrIdx.getRegSlot()) {
1650 if (!isEndValid && !LII->end.isBlock())
1651 LII->end = instrIdx.getRegSlot();
1658 bool isStartValid = getInstructionFromIndex(LII->start);
1659 if (!isStartValid && LII->end.isDead())
1670 while (Begin != MBB->begin() && !Indexes->hasIndex(*std::prev(Begin)))
1671 --Begin;
1672 while (End != MBB->end() && !Indexes->hasIndex(*End))
1676 if (End == MBB->end())
1681 Indexes->repairIndexesInRange(MBB, Begin, End);
1683 // Make sure a live interval exists for all register operands in the range.
1686 --I;
1694 MRI->shouldTrackSubRegLiveness(Reg)) {
1698 // did not, throw away any old live interval so it will be
1702 // Similarly if a subreg def has no precise subrange match then
1705 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
1716 // Don't bother to repair a freshly calculated live interval.
1741 for (MCRegUnit Unit : TRI->regunits(Reg)) {
1743 if (VNInfo *VNI = LR->getVNInfoAt(Pos))
1744 LR->removeValNo(VNI);
1753 assert(VNI->def.getBaseIndex() == Pos.getBaseIndex());
1760 if (SVNI->def.getBaseIndex() == Pos.getBaseIndex())
1775 Register NewVReg = MRI->cloneVirtualRegister(Reg);
1784 LICalc->reset(MF, getSlotIndexes(), DomTree, &getVNInfoAllocator());
1785 LICalc->constructMainRangeFromSubranges(LI);