Lines Matching defs:OpInfo
58 void update(const TargetLowering::AsmOperandInfo &OpInfo) {
63 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
64 OpInfo.ConstraintType == TargetLowering::C_Other) {
65 if (OpInfo.Type == InlineAsm::isInput)
67 else if (OpInfo.Type == InlineAsm::isOutput)
69 else if (OpInfo.Type == InlineAsm::isClobber)
82 GISelAsmOperandInfo &OpInfo,
89 if (OpInfo.ConstraintType == TargetLowering::C_Memory)
104 if (OpInfo.isMatchingInputConstraint())
109 if (OpInfo.ConstraintVT != MVT::Other)
111 TLI.getNumRegisters(MF.getFunction().getContext(), OpInfo.ConstraintVT);
132 OpInfo.Regs.push_back(R);
137 TargetLowering::AsmOperandInfo &OpInfo) {
138 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
141 if (OpInfo.Codes.size() == 1) {
142 OpInfo.ConstraintCode = OpInfo.Codes[0];
143 OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode);
145 TargetLowering::ConstraintGroup G = TLI->getConstraintPreferences(OpInfo);
155 OpInfo.ConstraintCode = G[BestIdx].first;
156 OpInfo.ConstraintType = G[BestIdx].second;
160 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
164 Value *Val = OpInfo.CallOperandVal;
170 if (const char *Repl = TLI->LowerXConstraint(OpInfo.ConstraintVT)) {
171 OpInfo.ConstraintCode = Repl;
172 OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode);
239 GISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
242 if (OpInfo.hasArg()) {
243 OpInfo.CallOperandVal = const_cast<Value *>(Call.getArgOperand(ArgNo));
245 if (isa<BasicBlock>(OpInfo.CallOperandVal)) {
250 Type *OpTy = OpInfo.CallOperandVal->getType();
254 if (OpInfo.isIndirect) {
266 OpInfo.ConstraintVT =
269 } else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
272 OpInfo.ConstraintVT =
276 OpInfo.ConstraintVT =
281 assert(OpInfo.Type != InlineAsm::isLabel &&
283 OpInfo.ConstraintVT = MVT::Other;
286 if (OpInfo.ConstraintVT == MVT::i64x8)
290 computeConstraintToUse(TLI, OpInfo);
293 ExtraInfo.update(OpInfo);
310 for (auto &OpInfo : ConstraintOperands) {
312 OpInfo.isMatchingInputConstraint()
313 ? ConstraintOperands[OpInfo.getMatchedOperand()]
314 : OpInfo;
317 getRegistersForValue(MF, MIRBuilder, OpInfo, RefOpInfo);
319 switch (OpInfo.Type) {
321 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
323 TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
333 GetOrCreateVRegs(*OpInfo.CallOperandVal);
341 assert(OpInfo.ConstraintType == TargetLowering::C_Register ||
342 OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
343 OpInfo.ConstraintType == TargetLowering::C_Other);
346 if (OpInfo.Regs.empty()) {
354 InlineAsm::Flag Flag(OpInfo.isEarlyClobber
357 OpInfo.Regs.size());
358 if (OpInfo.Regs.front().isVirtual()) {
363 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
369 for (Register Reg : OpInfo.Regs) {
372 (OpInfo.isEarlyClobber ? RegState::EarlyClobber : 0));
376 OutputOperands.push_back(OpInfo);
382 if (OpInfo.isMatchingInputConstraint()) {
383 unsigned DefIdx = OpInfo.getMatchedOperand();
405 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
426 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
427 OpInfo.isIndirect) {
433 if (OpInfo.ConstraintType == TargetLowering::C_Immediate ||
434 OpInfo.ConstraintType == TargetLowering::C_Other) {
437 if (!lowerAsmOperandForConstraint(OpInfo.CallOperandVal,
438 OpInfo.ConstraintCode, Ops,
441 << OpInfo.ConstraintCode << " yet\n");
456 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
458 if (!OpInfo.isIndirect) {
464 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
467 TLI->getInlineAsmMemConstraint(OpInfo.ConstraintCode);
472 GetOrCreateVRegs(*OpInfo.CallOperandVal);
480 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
481 OpInfo.ConstraintType == TargetLowering::C_Register) &&
484 if (OpInfo.isIndirect) {
487 << OpInfo.ConstraintCode << "'\n");
492 if (OpInfo.Regs.empty()) {
499 unsigned NumRegs = OpInfo.Regs.size();
500 ArrayRef<Register> SourceRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal);
512 if (OpInfo.Regs.front().isVirtual()) {
514 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
518 if (!buildAnyextOrCopy(OpInfo.Regs[0], SourceRegs[0], MIRBuilder))
520 Inst.addReg(OpInfo.Regs[0]);
526 const unsigned NumRegs = OpInfo.Regs.size();
531 for (Register Reg : OpInfo.Regs) {
570 GISelAsmOperandInfo &OpInfo = OutputOperands[i];
572 if (OpInfo.Regs.empty())
575 switch (OpInfo.ConstraintType) {
578 if (OpInfo.Regs.size() > 1) {
584 Register SrcReg = OpInfo.Regs[0];