Lines Matching defs:MIRBuilder
301 MachineIRBuilder &MIRBuilder) {
315 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
320 MachineIRBuilder &MIRBuilder) {
328 MIRBuilder.buildInstr(Opcode, {Res}, {Op0}, Flags);
332 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
333 return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder);
337 MachineIRBuilder &MIRBuilder) {
344 MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
346 MIRBuilder.buildCopy(
349 MIRBuilder.buildCopy(
355 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, Flags);
361 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
374 &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
380 return CLI->lowerReturn(MIRBuilder, Ret, VRegs, FuncInfo, SwiftErrorVReg);
577 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
579 auto &CurMBB = MIRBuilder.getMBB();
586 MIRBuilder.buildBr(*Succ0MBB);
1333 MachineIRBuilder &MIRBuilder) {
1337 MIRBuilder.buildBrIndirect(Tgt);
1341 MachineBasicBlock &CurBB = MIRBuilder.getMBB();
1362 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
1380 SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(), Ptr);
1381 MIRBuilder.buildCopy(Regs[0], VReg);
1398 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
1406 MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
1412 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
1427 Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
1429 MIRBuilder.buildCopy(VReg, Vals[0]);
1437 MIRBuilder.materializePtrAdd(Addr, Base, OffsetTy, Offsets[i] / 8);
1445 MIRBuilder.buildStore(Vals[i], Addr, *MMO);
1475 MachineIRBuilder &MIRBuilder) {
1490 MachineIRBuilder &MIRBuilder) {
1510 MachineIRBuilder &MIRBuilder) {
1521 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags);
1528 MachineIRBuilder &MIRBuilder) {
1537 MIRBuilder.buildCopy(Regs[0], Src);
1543 MachineIRBuilder &MIRBuilder) {
1551 MIRBuilder);
1552 return translateCopy(U, *U.getOperand(0), MIRBuilder);
1555 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
1559 MachineIRBuilder &MIRBuilder) {
1570 MIRBuilder.buildInstr(Opcode, {Res}, {Op}, Flags);
1575 MachineIRBuilder &MIRBuilder) {
1603 BaseReg = MIRBuilder
1634 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
1635 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0))
1644 IdxReg = MIRBuilder
1650 IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
1657 auto ElementSizeMIB = MIRBuilder.buildConstant(
1660 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0);
1664 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0);
1670 MIRBuilder.buildConstant(OffsetTy, Offset);
1675 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0),
1680 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
1685 MachineIRBuilder &MIRBuilder,
1708 SizeOpReg = MIRBuilder.buildZExtOrTrunc(SizeTy, SizeOpReg).getReg(0);
1710 auto ICall = MIRBuilder.buildInstr(Opcode);
1776 MachineIRBuilder &MIRBuilder,
1783 MIRBuilder.buildInstr(Opcode, {}, ArrayRef<llvm::SrcOp>{Code});
1785 MIRBuilder.buildInstr(Opcode);
1798 return CLI->lowerCall(MIRBuilder, Info);
1802 const CallInst &CI, MachineIRBuilder &MIRBuilder) {
1811 MIRBuilder.buildShuffleVector(Res, Op0, Op1,
1818 const CallInst &CI, MachineIRBuilder &MIRBuilder) {
1824 auto Undef = MIRBuilder.buildUndef(MRI->getType(Op));
1828 MIRBuilder.buildShuffleVector(Res[0], Op, Undef,
1830 MIRBuilder.buildShuffleVector(Res[1], Op, Undef,
1837 MachineIRBuilder &MIRBuilder) {
1841 MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD, {DstReg}, {});
1859 MachineIRBuilder &MIRBuilder) {
1861 MIRBuilder.buildInstr(
1869 MachineIRBuilder &MIRBuilder) {
1874 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale });
2013 MachineIRBuilder &MIRBuilder) {
2026 MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
2056 const ConstrainedFPIntrinsic &FPI, MachineIRBuilder &MIRBuilder) {
2071 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags);
2091 MachineIRBuilder &MIRBuilder) {
2113 MIRBuilder.buildDirectDbgValue(*PhysReg, Var, Expr);
2133 const CallInst &CI, Intrinsic::ID ID, MachineIRBuilder &MIRBuilder) {
2134 MachineInstrBuilder MIB = MIRBuilder.buildInstr(getConvOpcode(ID));
2150 MachineIRBuilder &MIRBuilder) {
2162 if (translateSimpleIntrinsic(CI, ID, MIRBuilder))
2192 MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI));
2200 DI.getExpression(), DI.getDebugLoc(), MIRBuilder);
2208 MIRBuilder.getDebugLoc()) &&
2211 MIRBuilder.buildDbgLabel(DI.getLabel());
2223 MIRBuilder.buildInstr(TargetOpcode::G_VASTART, {}, {getOrCreateVReg(*Ptr)})
2240 DI.getExpression(), DI.getDebugLoc(), MIRBuilder);
2244 return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
2246 return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
2248 return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
2250 return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
2252 return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
2254 return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
2256 return translateBinaryOp(TargetOpcode::G_UADDSAT, CI, MIRBuilder);
2258 return translateBinaryOp(TargetOpcode::G_SADDSAT, CI, MIRBuilder);
2260 return translateBinaryOp(TargetOpcode::G_USUBSAT, CI, MIRBuilder);
2262 return translateBinaryOp(TargetOpcode::G_SSUBSAT, CI, MIRBuilder);
2264 return translateBinaryOp(TargetOpcode::G_USHLSAT, CI, MIRBuilder);
2266 return translateBinaryOp(TargetOpcode::G_SSHLSAT, CI, MIRBuilder);
2268 return translateBinaryOp(TargetOpcode::G_UMIN, CI, MIRBuilder);
2270 return translateBinaryOp(TargetOpcode::G_UMAX, CI, MIRBuilder);
2272 return translateBinaryOp(TargetOpcode::G_SMIN, CI, MIRBuilder);
2274 return translateBinaryOp(TargetOpcode::G_SMAX, CI, MIRBuilder);
2277 return translateUnaryOp(TargetOpcode::G_ABS, CI, MIRBuilder);
2279 return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIX, CI, MIRBuilder);
2281 return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIX, CI, MIRBuilder);
2283 return translateFixedPointIntrinsic(TargetOpcode::G_SMULFIXSAT, CI, MIRBuilder);
2285 return translateFixedPointIntrinsic(TargetOpcode::G_UMULFIXSAT, CI, MIRBuilder);
2287 return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIX, CI, MIRBuilder);
2289 return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIX, CI, MIRBuilder);
2291 return translateFixedPointIntrinsic(TargetOpcode::G_SDIVFIXSAT, CI, MIRBuilder);
2293 return translateFixedPointIntrinsic(TargetOpcode::G_UDIVFIXSAT, CI, MIRBuilder);
2305 MIRBuilder.buildFMA(Dst, Op0, Op1, Op2,
2309 auto FMul = MIRBuilder.buildFMul(
2311 MIRBuilder.buildFAdd(Dst, FMul, Op2,
2318 MIRBuilder.buildFPExt(getOrCreateVReg(CI),
2324 MIRBuilder.buildFPTrunc(getOrCreateVReg(CI),
2330 MIRBuilder.buildFFrexp(VRegs[0], VRegs[1],
2336 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY_INLINE);
2338 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMCPY);
2340 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMMOVE);
2342 return translateMemFunc(CI, MIRBuilder, TargetOpcode::G_MEMSET);
2347 MIRBuilder.buildConstant(Reg, TypeID);
2357 getStackGuard(getOrCreateVReg(CI), MIRBuilder);
2364 getStackGuard(GuardVal, MIRBuilder);
2372 MIRBuilder.buildStore(
2381 MIRBuilder.buildInstr(TargetOpcode::G_STACKSAVE, {getOrCreateVReg(CI)}, {});
2385 MIRBuilder.buildInstr(TargetOpcode::G_STACKRESTORE, {},
2398 MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(CI)},
2405 MIRBuilder.buildUndef(Undef);
2416 MIRBuilder.buildCopy(getOrCreateVReg(CI),
2429 MIRBuilder
2436 MIRBuilder.buildInstr(TargetOpcode::G_WRITE_REGISTER)
2458 MIRBuilder.buildInstrNoInsert(TargetOpcode::LOCAL_ESCAPE)
2480 MIRBuilder.buildInstr(Opc, {Dst}, {ScalarSrc, VecSrc},
2495 auto Rdx = MIRBuilder.buildInstr(
2497 MIRBuilder.buildInstr(ScalarOpc, {Dst}, {ScalarSrc, Rdx},
2503 return translateTrap(CI, MIRBuilder, TargetOpcode::G_TRAP);
2505 return translateTrap(CI, MIRBuilder, TargetOpcode::G_DEBUGTRAP);
2507 return translateTrap(CI, MIRBuilder, TargetOpcode::G_UBSANTRAP);
2510 MIRBuilder.buildCopy(getOrCreateVReg(CI),
2514 return translateCallBase(CI, MIRBuilder);
2524 MIRBuilder
2536 MIRBuilder
2545 MIRBuilder.buildSetFPEnv(getOrCreateVReg(*FPEnv));
2549 MIRBuilder.buildResetFPEnv();
2553 MIRBuilder.buildSetFPMode(getOrCreateVReg(*FPState));
2557 MIRBuilder.buildResetFPMode();
2560 MIRBuilder.buildVScale(getOrCreateVReg(CI), 1);
2564 MIRBuilder.buildSCmp(getOrCreateVReg(CI),
2569 MIRBuilder.buildUCmp(getOrCreateVReg(CI),
2583 MIRBuilder.buildPrefetch(getOrCreateVReg(*Addr), RW, Locality, CacheType,
2593 LLT ResTy = getLLTForType(*Op0->getType(), MIRBuilder.getDataLayout());
2598 return translateVectorInterleave2Intrinsic(CI, MIRBuilder);
2600 return translateVectorDeinterleave2Intrinsic(CI, MIRBuilder);
2607 MIRBuilder);
2611 return translateConvergenceControlIntrinsic(CI, ID, MIRBuilder);
2617 MachineIRBuilder &MIRBuilder) {
2628 MIRBuilder, CB, [&](const Value &Val) { return getOrCreateVRegs(Val); });
2632 MachineIRBuilder &MIRBuilder) {
2643 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
2644 &CB, &MIRBuilder.getMBB(), Arg));
2647 SwiftError.getOrCreateVRegDefAt(&CB, &MIRBuilder.getMBB(), Arg);
2693 MIRBuilder, CB, Res, Args, SwiftErrorVReg, PAI, ConvergenceCtrlToken,
2700 HasTailCall = TII->isTailCall(*std::prev(MIRBuilder.getInsertPt()));
2706 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
2727 return translateInlineAsm(CI, MIRBuilder);
2739 return translateCallBase(CI, MIRBuilder);
2743 if (translateKnownIntrinsic(CI, ID, MIRBuilder))
2752 MachineInstrBuilder MIB = MIRBuilder.buildIntrinsic(ID, ResultRegs);
2876 MachineIRBuilder &MIRBuilder) {
2915 MIRBuilder.buildInstr(TargetOpcode::G_INVOKE_REGION_START);
2917 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
2921 if (!translateInlineAsm(I, MIRBuilder))
2923 } else if (!translateCallBase(I, MIRBuilder))
2929 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
2934 MachineBasicBlock *InvokeMBB = &MIRBuilder.getMBB();
2958 MIRBuilder.buildBr(ReturnMBB);
2963 MachineIRBuilder &MIRBuilder) {
2969 MachineIRBuilder &MIRBuilder) {
2972 MachineBasicBlock &MBB = MIRBuilder.getMBB();
2992 MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
3003 MIRBuilder.buildUndef(Undef);
3017 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
3025 MIRBuilder.buildCopy(PtrVReg, SelectorReg);
3026 MIRBuilder.buildCast(ResRegs[1], PtrVReg);
3032 MachineIRBuilder &MIRBuilder) {
3041 MIRBuilder.buildFrameIndex(Res, FI);
3055 MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
3064 MIRBuilder.buildMul(AllocSize, NumElts, TySize);
3070 auto SAMinusOne = MIRBuilder.buildConstant(IntPtrTy, StackAlign.value() - 1);
3071 auto AllocAdd = MIRBuilder.buildAdd(IntPtrTy, AllocSize, SAMinusOne,
3074 MIRBuilder.buildConstant(IntPtrTy, ~(uint64_t)(StackAlign.value() - 1));
3075 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst);
3080 MIRBuilder.buildDynStackAlloc(getOrCreateVReg(AI), AlignedAlloc, Alignment);
3087 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
3092 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)},
3098 bool IRTranslator::translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
3114 MIRBuilder.buildTrap();
3119 MachineIRBuilder &MIRBuilder) {
3124 return translateCopy(U, *U.getOperand(1), MIRBuilder);
3142 Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
3144 MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
3149 MachineIRBuilder &MIRBuilder) {
3153 return translateCopy(U, *U.getOperand(0), MIRBuilder);
3170 Idx = MIRBuilder.buildZExtOrTrunc(VecIdxTy, Idx).getReg(0);
3172 MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
3177 MachineIRBuilder &MIRBuilder) {
3184 auto SplatVal = MIRBuilder.buildExtractVectorElementConstant(
3187 MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal);
3197 MIRBuilder
3205 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
3210 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
3219 MachineIRBuilder &MIRBuilder) {
3231 MIRBuilder.buildAtomicCmpXchgWithSuccess(
3241 MachineIRBuilder &MIRBuilder) {
3306 MIRBuilder.buildAtomicRMW(
3316 MachineIRBuilder &MIRBuilder) {
3318 MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()),
3324 MachineIRBuilder &MIRBuilder) {
3332 MIRBuilder.buildFreeze(DstRegs[I], SrcRegs[I]);
3377 MachineIRBuilder &MIRBuilder) {
3381 MIRBuilder.setDebugLoc(DL);
3386 MIRBuilder.buildIndirectDbgValue(0, Variable, Expression);
3391 MIRBuilder.buildConstDbgValue(*CI, Variable, Expression);
3403 MIRBuilder.buildFIDbgValue(getOrCreateFrameIndex(*AI), Variable,
3408 MIRBuilder))
3415 MIRBuilder.buildDirectDbgValue(Reg, Variable, Expression);
3424 MachineIRBuilder &MIRBuilder) {
3443 MIRBuilder))
3448 MIRBuilder.setDebugLoc(DL);
3449 MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
3455 MachineIRBuilder &MIRBuilder) {
3458 MIRBuilder.setDebugLoc(DLR->getDebugLoc());
3461 MIRBuilder.getDebugLoc()) &&
3463 MIRBuilder.buildDbgLabel(DLR->getLabel());
3472 DVR.getDebugLoc(), MIRBuilder);
3475 DVR.getDebugLoc(), MIRBuilder);
3736 if (!CLI->lowerCall(MIRBuilder, Info)) {