Lines Matching defs:U
300 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
306 Register Op0 = getOrCreateVReg(*U.getOperand(0));
307 Register Op1 = getOrCreateVReg(*U.getOperand(1));
308 Register Res = getOrCreateVReg(U);
310 if (isa<Instruction>(U)) {
311 const Instruction &I = cast<Instruction>(U);
319 bool IRTranslator::translateUnaryOp(unsigned Opcode, const User &U,
321 Register Op0 = getOrCreateVReg(*U.getOperand(0));
322 Register Res = getOrCreateVReg(U);
324 if (isa<Instruction>(U)) {
325 const Instruction &I = cast<Instruction>(U);
332 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
333 return translateUnaryOp(TargetOpcode::G_FNEG, U, MIRBuilder);
336 bool IRTranslator::translateCompare(const User &U,
338 auto *CI = cast<CmpInst>(&U);
339 Register Op0 = getOrCreateVReg(*U.getOperand(0));
340 Register Op1 = getOrCreateVReg(*U.getOperand(1));
341 Register Res = getOrCreateVReg(U);
347 Res, getOrCreateVReg(*Constant::getNullValue(U.getType())));
350 Res, getOrCreateVReg(*Constant::getAllOnesValue(U.getType())));
361 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
362 const ReturnInst &RI = cast<ReturnInst>(U);
577 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
578 const BranchInst &BrInst = cast<BranchInst>(U);
691 bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) {
694 const SwitchInst &SI = cast<SwitchInst>(U);
841 assert(JT.Reg != -1U && "Should lower JT Header first!");
1332 bool IRTranslator::translateIndirectBr(const User &U,
1334 const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
1362 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
1363 const LoadInst &LI = cast<LoadInst>(U);
1412 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
1413 const StoreInst &SI = cast<StoreInst>(U);
1450 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
1451 const Value *Src = U.getOperand(0);
1452 Type *Int32Ty = Type::getInt32Ty(U.getContext());
1459 if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
1462 } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
1466 for (unsigned i = 1; i < U.getNumOperands(); ++i)
1467 Indices.push_back(U.getOperand(i));
1474 bool IRTranslator::translateExtractValue(const User &U,
1476 const Value *Src = U.getOperand(0);
1477 uint64_t Offset = getOffsetFromIndices(U, *DL);
1481 auto &DstRegs = allocateVRegs(U);
1489 bool IRTranslator::translateInsertValue(const User &U,
1491 const Value *Src = U.getOperand(0);
1492 uint64_t Offset = getOffsetFromIndices(U, *DL);
1493 auto &DstRegs = allocateVRegs(U);
1494 ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
1496 ArrayRef<Register> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
1509 bool IRTranslator::translateSelect(const User &U,
1511 Register Tst = getOrCreateVReg(*U.getOperand(0));
1512 ArrayRef<Register> ResRegs = getOrCreateVRegs(U);
1513 ArrayRef<Register> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
1514 ArrayRef<Register> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
1517 if (const SelectInst *SI = dyn_cast<SelectInst>(&U))
1527 bool IRTranslator::translateCopy(const User &U, const Value &V,
1530 auto &Regs = *VMap.getVRegs(U);
1533 VMap.getOffsets(U)->push_back(0);
1542 bool IRTranslator::translateBitCast(const User &U,
1545 if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
1546 getLLTForType(*U.getType(), *DL)) {
1549 if (isa<ConstantInt>(U.getOperand(0)))
1550 return translateCast(TargetOpcode::G_CONSTANT_FOLD_BARRIER, U,
1552 return translateCopy(U, *U.getOperand(0), MIRBuilder);
1555 return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
1558 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
1560 if (U.getType()->getScalarType()->isBFloatTy() ||
1561 U.getOperand(0)->getType()->getScalarType()->isBFloatTy())
1565 if (const Instruction *I = dyn_cast<Instruction>(&U))
1568 Register Op = getOrCreateVReg(*U.getOperand(0));
1569 Register Res = getOrCreateVReg(U);
1574 bool IRTranslator::translateGetElementPtr(const User &U,
1576 Value &Op0 = *U.getOperand(0);
1584 if (const Instruction *I = dyn_cast<Instruction>(&U))
1594 if (auto *VT = dyn_cast<VectorType>(U.getType())) {
1614 for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
1672 if (int64_t(Offset) >= 0 && cast<GEPOperator>(U).isInBounds())
1675 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0),
1680 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
2706 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
2707 const CallInst &CI = cast<CallInst>(U);
2723 if (isa<GCStatepointInst, GCRelocateInst, GCResultInst>(U))
2875 bool IRTranslator::translateInvoke(const User &U,
2877 const InvokeInst &I = cast<InvokeInst>(U);
2962 bool IRTranslator::translateCallBr(const User &U,
2968 bool IRTranslator::translateLandingPad(const User &U,
2970 const LandingPadInst &LP = cast<LandingPadInst>(U);
3031 bool IRTranslator::translateAlloca(const User &U,
3033 auto &AI = cast<AllocaInst>(U);
3087 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
3092 MIRBuilder.buildInstr(TargetOpcode::G_VAARG, {getOrCreateVReg(U)},
3093 {getOrCreateVReg(*U.getOperand(0)),
3094 DL->getABITypeAlign(U.getType()).value()});
3098 bool IRTranslator::translateUnreachable(const User &U, MachineIRBuilder &MIRBuilder) {
3102 auto &UI = cast<UnreachableInst>(U);
3118 bool IRTranslator::translateInsertElement(const User &U,
3122 if (auto *FVT = dyn_cast<FixedVectorType>(U.getType());
3124 return translateCopy(U, *U.getOperand(1), MIRBuilder);
3126 Register Res = getOrCreateVReg(U);
3127 Register Val = getOrCreateVReg(*U.getOperand(0));
3128 Register Elt = getOrCreateVReg(*U.getOperand(1));
3131 if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(2))) {
3139 Idx = getOrCreateVReg(*U.getOperand(2));
3148 bool IRTranslator::translateExtractElement(const User &U,
3152 if (cast<FixedVectorType>(U.getOperand(0)->getType())->getNumElements() == 1)
3153 return translateCopy(U, *U.getOperand(0), MIRBuilder);
3155 Register Res = getOrCreateVReg(U);
3156 Register Val = getOrCreateVReg(*U.getOperand(0));
3159 if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
3167 Idx = getOrCreateVReg(*U.getOperand(1));
3176 bool IRTranslator::translateShuffleVector(const User &U,
3182 if (U.getOperand(0)->getType()->isScalableTy()) {
3183 Value *Op0 = U.getOperand(0);
3187 MIRBuilder.buildSplatVector(getOrCreateVReg(U), SplatVal);
3192 if (auto *SVI = dyn_cast<ShuffleVectorInst>(&U))
3195 Mask = cast<ConstantExpr>(U).getShuffleMask();
3198 .buildInstr(TargetOpcode::G_SHUFFLE_VECTOR, {getOrCreateVReg(U)},
3199 {getOrCreateVReg(*U.getOperand(0)),
3200 getOrCreateVReg(*U.getOperand(1))})
3205 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
3206 const PHINode &PI = cast<PHINode>(U);
3218 bool IRTranslator::translateAtomicCmpXchg(const User &U,
3220 const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
3240 bool IRTranslator::translateAtomicRMW(const User &U,
3242 const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
3315 bool IRTranslator::translateFence(const User &U,
3317 const FenceInst &Fence = cast<FenceInst>(U);
3323 bool IRTranslator::translateFreeze(const User &U,
3325 const ArrayRef<Register> DstRegs = getOrCreateVRegs(U);
3326 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0));