Lines Matching defs:RegsToVisit

3702   SmallVector<Register, 8> RegsToVisit;
3725       RegsToVisit.push_back(OrLHS);
3729       RegsToVisit.push_back(OrRHS);
3734   if (RegsToVisit.empty() || RegsToVisit.size() % 2 != 0)
3736   return RegsToVisit;
3777     const SmallVector<Register, 8> &RegsToVisit, const unsigned MemSizeInBits) {
3779   // Each load found for the pattern. There should be one for each RegsToVisit.
3809   for (auto Reg : RegsToVisit) {
3881   assert(Loads.size() == RegsToVisit.size() &&
3934   auto RegsToVisit = findCandidatesForLoadOrCombine(&MI);
3935   if (!RegsToVisit)
3941   const unsigned NarrowMemSizeInBits = WideMemSizeInBits / RegsToVisit->size();
3956       MemOffset2Idx, *RegsToVisit, NarrowMemSizeInBits);