Lines Matching defs:TRI
92 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) {
93 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
94 return TRI.getSpillSize(*RC);
113 const TargetRegisterInfo &TRI) {
115 int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false);
128 if (It->readsRegister(Reg, &TRI) && !Use)
130 if (It->modifiesRegister(Reg, &TRI)) {
145 if (getRegisterSize(TRI, Reg) != getRegisterSize(TRI, SrcReg))
149 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI)
211 const TargetRegisterInfo &TRI;
235 FrameIndexesCache(MachineFrameInfo &MFI, const TargetRegisterInfo &TRI)
236 : MFI(MFI), TRI(TRI) {}
261 << printReg(Reg, &TRI) << " at "
268 unsigned Size = getRegisterSize(TRI, Reg);
292 << printReg(Reg, &TRI) << " at landing pad "
306 return getRegisterSize(TRI, A) > getRegisterSize(TRI, B);
319 const TargetRegisterInfo &TRI;
339 : MI(MI), MF(*MI.getMF()), TRI(*MF.getSubtarget().getRegisterInfo()),
394 LLVM_DEBUG(dbgs() << "Will spill " << printReg(Reg, &TRI) << " at index "
414 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, &TRI) << " to FI " << FI
420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI);
421 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
425 RC, &TRI, Register());
431 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
434 TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
442 TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
459 LLVM_DEBUG(dbgs() << "Reloading " << printReg(Reg, &TRI) << " from FI "
522 MIB.addImm(getRegisterSize(TRI, MO.getReg()));
549 MF.getMachineMemOperand(PtrInfo, Flags, getRegisterSize(TRI, R),
566 const TargetRegisterInfo &TRI;
572 : MF(MF), TRI(*MF.getSubtarget().getRegisterInfo()),
573 CacheFI(MF.getFrameInfo(), TRI) {}
585 const uint32_t *Mask = TRI.getCallPreservedMask(MF, CC);