Lines Matching defs:Reg
92 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) {
93 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
105 // Reg - register we're about to spill
110 static Register performCopyPropagation(Register Reg,
114 // First check if statepoint itself uses Reg in non-meta operands.
115 int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false);
118 return Reg;
122 return Reg;
128 if (It->readsRegister(Reg, &TRI) && !Use)
130 if (It->modifiesRegister(Reg, &TRI)) {
137 return Reg;
140 if (!DestSrc || DestSrc->Destination->getReg() != Reg)
141 return Reg;
145 if (getRegisterSize(TRI, Reg) != getRegisterSize(TRI, SrcReg))
146 return Reg;
149 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI)
182 // Record reload of Reg from FI in block MBB
183 void recordReload(Register Reg, int FI, const MachineBasicBlock *MBB) {
184 RegSlotPair RSP(Reg, FI);
190 // Does basic block MBB contains reload of Reg from FI?
191 bool hasReload(Register Reg, int FI, const MachineBasicBlock *MBB) {
192 RegSlotPair RSP(Reg, FI);
251 int getFrameIndex(Register Reg, MachineBasicBlock *EHPad) {
252 // Check if slot for Reg is already reserved at EHPad.
257 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; });
261 << printReg(Reg, &TRI) << " at "
268 unsigned Size = getRegisterSize(TRI, Reg);
288 // Remember assignment {Reg, FI} for EHPad
290 GlobalIndices[EHPad].push_back(std::make_pair(Reg, FI));
292 << printReg(Reg, &TRI) << " at landing pad "
367 bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; }
388 Register Reg = MO.getReg();
389 assert(Reg.isPhysical() && "Only physical regs are expected");
391 if (isCalleeSaved(Reg) && (AllowGCPtrInCSR || !GCRegs.contains(Reg)))
394 LLVM_DEBUG(dbgs() << "Will spill " << printReg(Reg, &TRI) << " at index "
397 if (VisitedRegs.insert(Reg).second)
398 RegsToSpill.push_back(Reg);
408 for (Register Reg : RegsToSpill) {
409 int FI = CacheFI.getFrameIndex(Reg, EHPad);
412 RegToSlotIdx[Reg] = FI;
414 LLVM_DEBUG(dbgs() << "Spilling " << printReg(Reg, &TRI) << " to FI " << FI
420 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI);
421 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
424 TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI,
429 void insertReloadBefore(unsigned Reg, MachineBasicBlock::iterator It,
431 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
432 int FI = RegToSlotIdx[Reg];
434 TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
442 TII.loadRegFromStackSlot(*MBB, It, Reg, FI, RC, &TRI, Register());
446 assert(TII.isLoadFromStackSlot(*Reload, Dummy) == Reg);
457 for (auto Reg : RegsToReload) {
458 insertReloadBefore(Reg, InsertPoint, MBB);
459 LLVM_DEBUG(dbgs() << "Reloading " << printReg(Reg, &TRI) << " from FI "
460 << RegToSlotIdx[Reg] << " after statepoint\n");
462 if (EHPad && !RC.hasReload(Reg, RegToSlotIdx[Reg], EHPad)) {
463 RC.recordReload(Reg, RegToSlotIdx[Reg], EHPad);
465 EHPad->SkipPHIsLabelsAndDebug(EHPad->begin(), Reg);
466 insertReloadBefore(Reg, EHPadInsertPoint, EHPad);
487 assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand");
488 Register Reg = DefMO.getReg();
495 MIB.addReg(Reg, RegState::Define);
500 assert(is_contained(RegsToSpill, Reg));
501 RegsToReload.push_back(Reg);
503 if (isCalleeSaved(Reg)) {
505 MIB.addReg(Reg, RegState::Define);
508 RegsToReload.push_back(Reg);