Lines Matching defs:Q
517 for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
518 const TargetRegisterClass *RC = Q.second.RC;
680 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
681 MachineInstr *UseMI = Q.second.Operand->getParent();
695 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
696 if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber())
699 MachineInstr *DefMI = Q.second.Operand->getParent();
923 for (const auto &Q : make_range(RegRefs.equal_range(CurrReg))) {
924 Q.second.Operand->setReg(NewReg);
928 const SUnit *SU = MISUnitMap[Q.second.Operand->getParent()];
930 UpdateDbgValues(DbgValues, Q.second.Operand->getParent(),