Lines Matching +full:per +full:- +full:processor
1 //===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent scheduling interfaces which should
14 // 2. Scheduler Read/Write resources for simple per-opcode cost model.
21 // (2) A per-operand machine model can be implemented in any
24 // A. Associate per-operand SchedReadWrite types with Instructions by
27 // processor resources and latency with each SchedReadWrite type.
31 // per-operand SchedReadWrite types. Unlike method A, these types may
45 // a machine-independent SchedReadWrite type to map to a sequence of
46 // machine-dependent types.
48 // (3) A per-pipeline-stage machine model can be implemented by providing
50 //===----------------------------------------------------------------------===//
68 // properties are defined in MCSchedModel. A value of "-1" in the
77 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
78 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
79 int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for
81 int LoadLatency = -1; // Cycles for loads to access the cache.
82 int HighLatency = -1; // Approximation of cycles for "high latency" ops.
83 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
85 // Per-cycle resources tables.
105 // A processor may only implement part of published ISA, due to either new ISA
109 // For a processor which doesn't support some feature(s), the schedule model
132 // Define a kind of processor resource that may be common across
136 // Define a number of interchangeable processor resources. NumUnits
144 // out-of-order engine. Buffered resources may be held for multiple
147 // changes this to an in-order issue/dispatch resource. In this case,
149 // issues in-order, forcing a stall whenever a subsequent instruction
152 // an in-order latency resource. In this case, the scheduler models
156 // Examples (all assume an out-of-order engine):
158 // Use BufferSize = -1 for "issue ports" fed by a unified reservation
166 // differently. Here we refer to stage between decoding into micro-ops
172 // Use BufferSize = 1 for in-order execution units. This is used for
173 // an in-order pipeline within an out-of-order core where scheduling
174 // dependent operations back-to-back is guaranteed to cause a
175 // bubble. e.g. Cortex-a9 floating-point.
177 // Use BufferSize > 1 for out-of-order executions units with a
181 // To model both dispatch/issue groups and in-order execution units,
185 // SchedModel ties these units to a processor for any stand-alone defs
191 int BufferSize = -1;
195 // Subtargets typically define processor resource kind and number of
203 int BufferSize = -1;
210 // List the per-operand types that map to the machine model of an
217 // two-address instruction could have two tied operands or single
249 // SchedModel ties these resources to a processor.
264 // Allow a processor to mark some scheduling classes as unsupported
267 // Allow a processor to mark some scheduling classes as single-issue.
270 // An instruction is allowed to retire out-of-order if RetireOOO is
272 // MCA for in-order subtargets, and is ignored for other targets.
280 // defined by the subtarget, and maps the SchedWrite to processor
285 // them to processor resources in one place. Then ItinRW can map
298 // By default, each SchedWrite takes one micro-op, which is counted
299 // against the processor's IssueWidth limit. If an instruction can
300 // write multiple registers with a single micro-op, the subtarget
301 // should define one of the writes to be zero micro-ops. If a
302 // subtarget requires multiple micro-ops to write a single result, it
307 // operands. The scheduler assumes that all micro-ops must be
308 // dispatched in the same cycle. These micro-ops may be required to
323 // SchedModel ties these resources to a processor.
327 // Allow a processor to mark some scheduling classes as unsupported
333 // A processor may define a ReadAdvance associated with a SchedRead
335 // effectively increases latency, which may be used for cross-domain
376 // if-statement's expression. Available variables are MI, SchedModel,
387 // MCSchedPredicate, this is the default scheduling case used by llvm-mca.
418 // per-operand instead of the usual sequential writes feeding a single
436 // SchedModel ties this opcode mapping to a processor.
449 // SchedModel ties this ItineraryClass mapping to a processor.
456 // Alias a target-defined SchedReadWrite to a processor specific
462 // and ties this SchedAlias mapping to a processor.
469 // Allow the definition of processor register files for register renaming
472 // Each processor register file declares:
473 // - The set of registers that can be renamed.
474 // - The number of physical registers which can be used for register renaming
476 // - The cost of a register rename.
477 // - The set of registers that allow move elimination.
478 // - The maximum number of moves that can be eliminated every cycle.
479 // - Whether move elimination is limited to register moves whose input
496 // A sub-register V of register R is implicitly part of the same register file.
498 // Otherwise, the processor keeps it (as well as any other different part
509 // There is also no penalty for writes that "clear the content a super-register"
510 // (see MC/MCInstrAnalysis.h - method MCInstrAnalysis::clearsSuperRegisters()).
511 // On x86-64, 32-bit GPR writes implicitly zero the upper half of the underlying
516 // renames per cycle, which might not be true for all hardware or register
524 // partial write is combined with the previous super-register definition. We
541 // - MI is a move elimination candidate.
542 // - The destination register is from a register class that allows move
544 // - Constraints on the move kind, and the maximum number of moves that can be
545 // eliminated per cycle are all met.
562 // A value less-than-or-equal-to zero for field 'ReorderBufferSize' means: "the
563 // size is unknown". The idea is that external tools can fall-back to using
566 // restrictions on the number of instructions retired per cycle".
567 // Models can optionally specify up to one instance of RetireControlUnit per
575 // Base class for Load/StoreQueue. It is used to identify processor resources