Lines Matching defs:ArchSpec
1 //===-- ArchSpec.cpp ------------------------------------------------------===//
9 #include "lldb/Utility/ArchSpec.h"
25 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
36 ArchSpec::Core core;
42 // This core information can be looked using the ArchSpec::Core as the index
44 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
46 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
48 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
50 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
52 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
54 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
56 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
58 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
60 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
62 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
64 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
66 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
68 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
70 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
72 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
74 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
76 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
78 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
80 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
82 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
84 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
86 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
88 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
90 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
92 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
94 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
96 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
98 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
101 ArchSpec::eCore_arm_arm64, "arm64"},
103 ArchSpec::eCore_arm_armv8, "armv8"},
104 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
107 ArchSpec::eCore_arm_arm64e, "arm64e"},
109 ArchSpec::eCore_arm_arm64_32, "arm64_32"},
111 ArchSpec::eCore_arm_aarch64, "aarch64"},
114 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
116 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
118 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
120 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
122 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
124 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
127 ArchSpec::eCore_mips32r2el, "mipsr2el"},
129 ArchSpec::eCore_mips32r3el, "mipsr3el"},
131 ArchSpec::eCore_mips32r5el, "mipsr5el"},
133 ArchSpec::eCore_mips32r6el, "mipsr6el"},
136 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
138 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
140 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
142 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
144 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
147 ArchSpec::eCore_mips64el, "mips64el"},
149 ArchSpec::eCore_mips64r2el, "mips64r2el"},
151 ArchSpec::eCore_mips64r3el, "mips64r3el"},
153 ArchSpec::eCore_mips64r5el, "mips64r5el"},
155 ArchSpec::eCore_mips64r6el, "mips64r6el"},
158 {eByteOrderLittle, 2, 2, 4, llvm::Triple::msp430, ArchSpec::eCore_msp430,
161 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
163 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
165 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
167 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
169 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
171 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
173 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
175 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
177 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
179 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
181 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
183 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
185 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
189 ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
190 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
193 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
196 ArchSpec::eCore_s390x_generic, "s390x"},
199 ArchSpec::eCore_sparc_generic, "sparc"},
201 ArchSpec::eCore_sparc9_generic, "sparcv9"},
203 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
205 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
208 ArchSpec::eCore_x86_32_i486sx, "i486sx"},
209 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
213 ArchSpec::eCore_x86_64_x86_64, "x86_64"},
215 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
217 ArchSpec::eCore_hexagon_generic, "hexagon"},
219 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
221 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
223 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
225 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
229 ArchSpec::eCore_loongarch32, "loongarch32"},
231 ArchSpec::eCore_loongarch64, "loongarch64"},
234 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
236 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
237 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
239 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
241 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
247 // ArchSpec::Core enumeration.
249 ArchSpec::kNumCores,
253 ArchSpec::Core core;
267 void ArchSpec::ListSupportedArchNames(StringList &list) {
272 void ArchSpec::AutoComplete(CompletionRequest &request) {
288 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
289 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
290 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
291 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
292 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
293 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
294 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
295 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
296 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
297 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
298 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
299 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
300 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
301 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
302 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
303 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
304 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
305 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
306 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
307 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
308 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
309 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
310 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
311 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
312 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
313 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
314 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
315 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
316 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
317 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
318 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
319 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
320 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
321 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
322 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
323 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
324 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
325 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
326 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
327 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
328 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
329 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
330 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
331 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
332 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
333 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
334 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
335 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
336 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
337 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
338 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
339 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
340 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
341 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
342 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
343 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
344 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
345 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
346 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
347 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
349 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
350 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
363 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
365 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
367 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
369 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
371 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
372 ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
373 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
374 ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
375 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
377 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
379 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
381 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
383 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
385 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
387 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
388 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
389 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
390 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
391 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
392 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
393 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
394 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
395 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
396 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
397 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
399 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
400 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
401 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
402 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
403 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
404 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
405 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
406 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
407 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
408 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
409 {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE,
411 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
413 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
415 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
417 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
418 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
419 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
420 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
421 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH,
422 ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu,
424 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH,
425 ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu,
437 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
439 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
441 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
443 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
445 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
447 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
449 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
451 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
488 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
510 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
525 ArchSpec::ArchSpec() = default;
527 ArchSpec::ArchSpec(const char *triple_cstr) {
532 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
534 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
536 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
540 ArchSpec::~ArchSpec() = default;
542 void ArchSpec::Clear() {
552 const char *ArchSpec::GetArchitectureName() const {
559 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
561 std::string ArchSpec::GetTargetABI() const {
566 switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
567 case ArchSpec::eMIPSABI_N64:
570 case ArchSpec::eMIPSABI_N32:
573 case ArchSpec::eMIPSABI_O32:
583 void ArchSpec::SetFlags(const std::string &elf_abi) {
588 flag |= ArchSpec::eMIPSABI_N64;
590 flag |= ArchSpec::eMIPSABI_N32;
592 flag |= ArchSpec::eMIPSABI_O32;
597 std::string ArchSpec::GetClangTargetCPU() const {
601 case ArchSpec::eCore_mips32:
602 case ArchSpec::eCore_mips32el:
605 case ArchSpec::eCore_mips32r2:
606 case ArchSpec::eCore_mips32r2el:
609 case ArchSpec::eCore_mips32r3:
610 case ArchSpec::eCore_mips32r3el:
613 case ArchSpec::eCore_mips32r5:
614 case ArchSpec::eCore_mips32r5el:
617 case ArchSpec::eCore_mips32r6:
618 case ArchSpec::eCore_mips32r6el:
621 case ArchSpec::eCore_mips64:
622 case ArchSpec::eCore_mips64el:
625 case ArchSpec::eCore_mips64r2:
626 case ArchSpec::eCore_mips64r2el:
629 case ArchSpec::eCore_mips64r3:
630 case ArchSpec::eCore_mips64r3el:
633 case ArchSpec::eCore_mips64r5:
634 case ArchSpec::eCore_mips64r5el:
637 case ArchSpec::eCore_mips64r6:
638 case ArchSpec::eCore_mips64r6el:
651 uint32_t ArchSpec::GetMachOCPUType() const {
663 uint32_t ArchSpec::GetMachOCPUSubType() const {
675 uint32_t ArchSpec::GetDataByteSize() const {
679 uint32_t ArchSpec::GetCodeByteSize() const {
683 llvm::Triple::ArchType ArchSpec::GetMachine() const {
691 uint32_t ArchSpec::GetAddressByteSize() const {
705 ByteOrder ArchSpec::GetDefaultEndian() const {
712 bool ArchSpec::CharIsSignedByDefault() const {
738 lldb::ByteOrder ArchSpec::GetByteOrder() const {
747 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
754 ArchSpec &arch) {
789 bool ArchSpec::SetTriple(llvm::StringRef triple) {
802 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
809 void ArchSpec::MergeFrom(const ArchSpec &other) {
836 // If this and other are both arm ArchSpecs and this ArchSpec is a generic
837 // "some kind of arm" spec but the other ArchSpec is a specific arm core,
841 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
842 other.GetCore() != ArchSpec::eCore_arm_generic) {
851 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
877 // the ArchSpec::TripleVendorWasSpecified() method says that any
927 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
934 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
972 bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
1049 void ArchSpec::UpdateCore() {
1066 void ArchSpec::CoreUpdated(bool update_triple) {
1082 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1088 case ArchSpec::kCore_any:
1091 case ArchSpec::eCore_arm_generic:
1095 case ArchSpec::kCore_arm_any:
1096 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1098 if (core2 >= ArchSpec::kCore_thumb_first &&
1099 core2 <= ArchSpec::kCore_thumb_last)
1101 if (core2 == ArchSpec::kCore_arm_any)
1105 case ArchSpec::kCore_x86_32_any:
1106 if ((core2 >= ArchSpec::kCore_x86_32_first &&
1107 core2 <= ArchSpec::kCore_x86_32_last) ||
1108 (core2 == ArchSpec::kCore_x86_32_any))
1112 case ArchSpec::kCore_x86_64_any:
1113 if ((core2 >= ArchSpec::kCore_x86_64_first &&
1114 core2 <= ArchSpec::kCore_x86_64_last) ||
1115 (core2 == ArchSpec::kCore_x86_64_any))
1119 case ArchSpec::kCore_ppc_any:
1120 if ((core2 >= ArchSpec::kCore_ppc_first &&
1121 core2 <= ArchSpec::kCore_ppc_last) ||
1122 (core2 == ArchSpec::kCore_ppc_any))
1126 case ArchSpec::kCore_ppc64_any:
1127 if ((core2 >= ArchSpec::kCore_ppc64_first &&
1128 core2 <= ArchSpec::kCore_ppc64_last) ||
1129 (core2 == ArchSpec::kCore_ppc64_any))
1133 case ArchSpec::kCore_hexagon_any:
1134 if ((core2 >= ArchSpec::kCore_hexagon_first &&
1135 core2 <= ArchSpec::kCore_hexagon_last) ||
1136 (core2 == ArchSpec::kCore_hexagon_any))
1144 case ArchSpec::eCore_arm_armv7em:
1146 if (core2 == ArchSpec::eCore_arm_generic)
1148 if (core2 == ArchSpec::eCore_arm_armv7m)
1150 if (core2 == ArchSpec::eCore_arm_armv6m)
1152 if (core2 == ArchSpec::eCore_arm_armv7)
1162 case ArchSpec::eCore_arm_armv7m:
1164 if (core2 == ArchSpec::eCore_arm_generic)
1166 if (core2 == ArchSpec::eCore_arm_armv6m)
1168 if (core2 == ArchSpec::eCore_arm_armv7)
1170 if (core2 == ArchSpec::eCore_arm_armv7em)
1180 case ArchSpec::eCore_arm_armv6m:
1182 if (core2 == ArchSpec::eCore_arm_generic)
1184 if (core2 == ArchSpec::eCore_arm_armv7em)
1186 if (core2 == ArchSpec::eCore_arm_armv7)
1188 if (core2 == ArchSpec::eCore_arm_armv6m)
1194 case ArchSpec::eCore_arm_armv7f:
1195 case ArchSpec::eCore_arm_armv7k:
1196 case ArchSpec::eCore_arm_armv7s:
1197 case ArchSpec::eCore_arm_armv7l:
1198 case ArchSpec::eCore_arm_armv8l:
1200 if (core2 == ArchSpec::eCore_arm_generic)
1202 if (core2 == ArchSpec::eCore_arm_armv7)
1208 case ArchSpec::eCore_x86_64_x86_64h:
1211 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1216 case ArchSpec::eCore_arm_armv8:
1218 if (core2 == ArchSpec::eCore_arm_arm64)
1220 if (core2 == ArchSpec::eCore_arm_aarch64)
1222 if (core2 == ArchSpec::eCore_arm_arm64e)
1228 case ArchSpec::eCore_arm_arm64e:
1230 if (core2 == ArchSpec::eCore_arm_arm64)
1232 if (core2 == ArchSpec::eCore_arm_aarch64)
1234 if (core2 == ArchSpec::eCore_arm_armv8)
1239 case ArchSpec::eCore_arm_aarch64:
1241 if (core2 == ArchSpec::eCore_arm_arm64)
1243 if (core2 == ArchSpec::eCore_arm_armv8)
1245 if (core2 == ArchSpec::eCore_arm_arm64e)
1251 case ArchSpec::eCore_arm_arm64:
1253 if (core2 == ArchSpec::eCore_arm_aarch64)
1255 if (core2 == ArchSpec::eCore_arm_armv8)
1257 if (core2 == ArchSpec::eCore_arm_arm64e)
1263 case ArchSpec::eCore_arm_arm64_32:
1265 if (core2 == ArchSpec::eCore_arm_generic)
1271 case ArchSpec::eCore_mips32:
1273 if (core2 >= ArchSpec::kCore_mips32_first &&
1274 core2 <= ArchSpec::kCore_mips32_last)
1280 case ArchSpec::eCore_mips32el:
1282 if (core2 >= ArchSpec::kCore_mips32el_first &&
1283 core2 <= ArchSpec::kCore_mips32el_last)
1289 case ArchSpec::eCore_mips64:
1291 if (core2 >= ArchSpec::kCore_mips32_first &&
1292 core2 <= ArchSpec::kCore_mips32_last)
1294 if (core2 >= ArchSpec::kCore_mips64_first &&
1295 core2 <= ArchSpec::kCore_mips64_last)
1301 case ArchSpec::eCore_mips64el:
1303 if (core2 >= ArchSpec::kCore_mips32el_first &&
1304 core2 <= ArchSpec::kCore_mips32el_last)
1306 if (core2 >= ArchSpec::kCore_mips64el_first &&
1307 core2 <= ArchSpec::kCore_mips64el_last)
1313 case ArchSpec::eCore_mips64r2:
1314 case ArchSpec::eCore_mips64r3:
1315 case ArchSpec::eCore_mips64r5:
1317 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1319 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1325 case ArchSpec::eCore_mips64r2el:
1326 case ArchSpec::eCore_mips64r3el:
1327 case ArchSpec::eCore_mips64r5el:
1329 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1331 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1337 case ArchSpec::eCore_mips32r2:
1338 case ArchSpec::eCore_mips32r3:
1339 case ArchSpec::eCore_mips32r5:
1341 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1346 case ArchSpec::eCore_mips32r2el:
1347 case ArchSpec::eCore_mips32r3el:
1348 case ArchSpec::eCore_mips32r5el:
1350 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1355 case ArchSpec::eCore_mips32r6:
1357 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1362 case ArchSpec::eCore_mips32r6el:
1364 if (core2 == ArchSpec::eCore_mips32el ||
1365 core2 == ArchSpec::eCore_mips32r6el)
1370 case ArchSpec::eCore_mips64r6:
1372 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1374 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1379 case ArchSpec::eCore_mips64r6el:
1381 if (core2 == ArchSpec::eCore_mips32el ||
1382 core2 == ArchSpec::eCore_mips32r6el)
1384 if (core2 == ArchSpec::eCore_mips64el ||
1385 core2 == ArchSpec::eCore_mips64r6el)
1398 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1399 const ArchSpec::Core lhs_core = lhs.GetCore();
1400 const ArchSpec::Core rhs_core = rhs.GetCore();
1405 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1409 bool ArchSpec::IsFullySpecifiedTriple() const {
1424 bool ArchSpec::IsAlwaysThumbInstructions() const {
1436 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1437 GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1438 GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1439 GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1440 GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1441 GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1451 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {