Lines Matching +full:0 +full:xf9000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
29 #define GPR_OFFSET_NAME(reg) 0
31 #define FPU_OFFSET_NAME(reg) 0
32 #define EXC_OFFSET_NAME(reg) 0
33 #define DBG_OFFSET_NAME(reg) 0
34 #define DBG_OFFSET_NAME(reg) 0
36 "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
61 #define No_VFP 0
77 static inline bool IsZero(uint64_t x) { return x == 0; }
85 if (shift == 0)
189 {0xff000000, 0xd1000000, No_VFP,
192 {0xff000000, 0xf1000000, No_VFP,
195 {0xff000000, 0x91000000, No_VFP,
198 {0xff000000, 0xb1000000, No_VFP,
202 {0xff000000, 0x51000000, No_VFP,
205 {0xff000000, 0x71000000, No_VFP,
208 {0xff000000, 0x11000000, No_VFP,
211 {0xff000000, 0x31000000, No_VFP,
215 {0xffc00000, 0x29000000, No_VFP,
218 {0xffc00000, 0xa9000000, No_VFP,
221 {0xffc00000, 0x2d000000, No_VFP,
224 {0xffc00000, 0x6d000000, No_VFP,
227 {0xffc00000, 0xad000000, No_VFP,
231 {0xffc00000, 0x29800000, No_VFP,
234 {0xffc00000, 0xa9800000, No_VFP,
237 {0xffc00000, 0x2d800000, No_VFP,
240 {0xffc00000, 0x6d800000, No_VFP,
243 {0xffc00000, 0xad800000, No_VFP,
247 {0xffc00000, 0x28800000, No_VFP,
250 {0xffc00000, 0xa8800000, No_VFP,
253 {0xffc00000, 0x2c800000, No_VFP,
256 {0xffc00000, 0x6c800000, No_VFP,
259 {0xffc00000, 0xac800000, No_VFP,
263 {0xffc00000, 0x29400000, No_VFP,
266 {0xffc00000, 0xa9400000, No_VFP,
269 {0xffc00000, 0x2d400000, No_VFP,
272 {0xffc00000, 0x6d400000, No_VFP,
275 {0xffc00000, 0xad400000, No_VFP,
279 {0xffc00000, 0x29c00000, No_VFP,
282 {0xffc00000, 0xa9c00000, No_VFP,
285 {0xffc00000, 0x2dc00000, No_VFP,
288 {0xffc00000, 0x6dc00000, No_VFP,
291 {0xffc00000, 0xadc00000, No_VFP,
295 {0xffc00000, 0x28c00000, No_VFP,
298 {0xffc00000, 0xa8c00000, No_VFP,
301 {0xffc00000, 0x2cc00000, No_VFP,
304 {0xffc00000, 0x6cc00000, No_VFP,
307 {0xffc00000, 0xacc00000, No_VFP,
311 {0xffe00c00, 0xb8000400, No_VFP,
314 {0xffe00c00, 0xf8000400, No_VFP,
317 {0xffe00c00, 0xb8000c00, No_VFP,
320 {0xffe00c00, 0xf8000c00, No_VFP,
323 {0xffc00000, 0xb9000000, No_VFP,
326 {0xffc00000, 0xf9000000, No_VFP,
330 {0xffe00c00, 0xb8400400, No_VFP,
333 {0xffe00c00, 0xf8400400, No_VFP,
336 {0xffe00c00, 0xb8400c00, No_VFP,
339 {0xffe00c00, 0xf8400c00, No_VFP,
342 {0xffc00000, 0xb9400000, No_VFP,
345 {0xffc00000, 0xf9400000, No_VFP,
349 {0xfc000000, 0x14000000, No_VFP, &EmulateInstructionARM64::EmulateB,
351 {0xff000010, 0x54000000, No_VFP, &EmulateInstructionARM64::EmulateBcond,
353 {0x7f000000, 0x34000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
355 {0x7f000000, 0x35000000, No_VFP, &EmulateInstructionARM64::EmulateCBZ,
357 {0x7f000000, 0x36000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
359 {0x7f000000, 0x37000000, No_VFP, &EmulateInstructionARM64::EmulateTBZ,
365 for (size_t i = 0; i < k_num_arm_opcodes; ++i) {
381 ReadMemoryUnsigned(read_inst_context, m_addr, 4, 0, &success),
407 uint32_t orig_pc_value = 0;
410 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
422 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
446 row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0);
475 #if 0
490 if target<55> == '0' && TCR_EL1.TBI0 == '1' then
498 _PC = target<63:0>;
530 case 0:
543 result = (m_opcode_pstate.C == 1 && m_opcode_pstate.Z == 0);
549 result = (m_opcode_pstate.N == m_opcode_pstate.V && m_opcode_pstate.Z == 0);
552 // Always execute (cond == 0b1110, or the special 0b1111 which gives
572 result = Bits64(result, N - 1, 0);
604 // carry_in = 0;
622 const uint32_t Rd = Bits32(opcode, 4, 0);
634 case 0:
645 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
703 uint32_t Rt = Bits32(opcode, 4, 0);
727 is_signed = (opc & 1) != 0;
797 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
800 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
824 context_t.SetRegisterToRegisterPlusOffset(*reg_info_Rt, *reg_info_base, 0);
835 error) == 0)
838 if (!WriteMemory(context_t, address + 0, buffer.data(),
849 error) == 0)
883 error) == 0)
901 error) == 0)
934 uint32_t t = Bits32(opcode, 4, 0);
960 if (Bit32(opc, 1) == 0) {
961 memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE;
964 if (size == 2 && Bit32(opc, 0) == 1)
975 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
978 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
1006 postindex ? 0 : offset);
1015 error) == 0)
1038 error) == 0)
1065 #if 0
1076 LLDB_REGNUM_GENERIC_PC, 0, &success);
1080 int64_t offset = llvm::SignExtend64<28>(Bits32(opcode, 25, 0) << 2);
1101 #if 0
1109 if (ConditionHolds(Bits32(opcode, 3, 0))) {
1113 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1130 #if 0
1133 boolean iszero = (op == '0');
1143 uint32_t t = Bits32(opcode, 4, 0);
1144 bool is_zero = Bit32(opcode, 24) == 0;
1148 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1152 if (m_ignore_conditions || ((operand == 0) == is_zero)) {
1154 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);
1168 #if 0
1178 uint32_t t = Bits32(opcode, 4, 0);
1184 ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
1190 eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC, 0, &success);