Lines Matching +full:0 +full:xf9000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
39 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
47 ::memset(®_info, 0, sizeof(RegisterInfo));
234 // FPA Registers 0-7
260 // Intel wireless MMX general purpose registers 0 - 7 XScale accumulator
261 // register 0 - 7 (they do overlap with wCGR0 - wCGR7)
287 // Intel wireless MMX data registers 0 - 15
423 // Intel wireless MMX control register in co-processor 0 - 7
604 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
609 return 0;
616 ITCounter = CountITSize(Bits32(bits7_0, 3, 0));
617 if (ITCounter == 0)
622 if (FirstCond == 0xF) {
625 if (FirstCond == 0xE && ITCounter != 1) {
637 if (ITCounter == 0)
638 ITState = 0;
640 unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1;
641 SetBits32(ITState, 4, 0, NewITState4_0);
646 bool ITSession::InITBlock() { return ITCounter != 0; }
660 #define REG_RD 0
665 #define PC_REGLIST_BIT 0x8000
667 #define ARMv4 (1u << 0)
678 #define ARMvAll (0xffffffffu)
694 #define No_VFP 0
775 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
893 #if 0
901 for (i = 0 to 14)
926 uint32_t registers = 0;
930 registers = Bits32(opcode, 7, 0);
940 registers = Bits32(opcode, 15, 0) & ~0xa000;
953 registers = Bits32(opcode, 15, 0);
976 for (i = 0; i < 15; ++i) {
1016 #if 0
1022 for i = 0 to 14
1030 if registers<13> == '0' then SP = SP + 4*BitCount(registers);
1042 uint32_t registers = 0;
1046 registers = Bits32(opcode, 7, 0);
1056 registers = Bits32(opcode, 15, 0) & ~0x2000;
1077 registers = Bits32(opcode, 15, 0);
1106 for (i = 0; i < 15; ++i) {
1109 data = MemARead(context, addr, 4, 0, &success);
1121 data = MemARead(context, addr, 4, 0, &success);
1144 #if 0
1149 (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1173 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
1205 #if 0
1248 context.SetRegisterPlusOffset(*sp_reg, 0);
1267 #if 0
1293 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
1300 Rd = Bits32(opcode, 2, 0);
1308 Rm = Bits32(opcode, 3, 0);
1320 Rm = Bits32(opcode, 3, 0);
1345 context.SetRegisterPlusOffset(*dwarf_reg, 0);
1358 #if 0
1380 0; // the carry bit after ThumbExpandImm_C or ARMExpandImm_C.
1382 // 0 to silence the static analyzer
1388 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
1410 uint32_t imm8 = Bits32(opcode, 7, 0);
1437 uint32_t imm12 = Bits32(opcode, 11, 0);
1471 #if 0
1477 R[d] = result<31:0>;
1497 d = Bits32(opcode, 2, 0);
1499 m = Bits32(opcode, 2, 0);
1512 m = Bits32(opcode, 3, 0);
1524 n = Bits32(opcode, 3, 0);
1547 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
1554 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
1561 // R[d] = result<31:0>;
1572 (0x0000ffff & result)))
1581 SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
1600 #if 0
1660 #if 0
1688 Rd = Bits32(opcode, 2, 0);
1692 shift_n = 0;
1698 Rm = Bits32(opcode, 3, 0);
1707 Rm = Bits32(opcode, 3, 0);
1741 #if 0
1750 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
1751 elsif UnalignedSupport() || address<1:0> = '00' then
1755 R[t] = ROR(data, 8*UInt(address<1:0>));
1772 context.SetRegisterPlusOffset(*pc_reg, 0);
1783 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1788 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1804 data = MemURead(context, address, 4, 0, &success);
1809 if (Bits32(address, 1, 0) == 0) {
1815 } else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) {
1829 #if 0
1834 (result, carry, overflow) = AddWithCarry(SP, imm32, '0');
1860 imm32 = (Bits32(opcode, 7, 0) << 2);
1882 // if d == 15 && S == "0" then UNPREDICTABLE;
1883 if (d == 15 && setflags == 0)
1894 uint32_t imm8 = Bits32(opcode, 7, 0);
1905 // (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
1906 AddWithCarryResult res = AddWithCarry(sp, imm32, 0);
1940 #if 0
1946 (result, carry, overflow) = AddWithCarry(SP, shifted, '0');
2000 #if 0
2036 uint32_t imm11 = Bits32(opcode, 10, 0);
2070 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2077 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 |
2104 #if 0
2142 Rm = Bits32(opcode, 3, 0);
2169 #if 0
2189 Rm = Bits32(opcode, 3, 0);
2217 #if 0
2222 if JMCR.JE == '0' || CurrentInstrSet() == InstrSet_ThumbEE then
2245 Rm = Bits32(opcode, 3, 0);
2270 #if 0
2320 #if 0
2373 #if 0
2459 #if 0
2488 imm12 = Bits32(opcode, 11, 0);
2553 #if 0
2561 for r = 0 to regs-1
2564 for r = 0 to regs-1
2567 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
2568 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
2588 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2590 regs = Bits32(opcode, 7, 0) / 2;
2591 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2592 if (regs == 0 || regs > 16 || (d + regs) > 32)
2599 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2600 regs = Bits32(opcode, 7, 0);
2601 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2602 if (regs == 0 || regs > 16 || (d + regs) > 32)
2619 for (i = 0; i < regs; ++i) {
2624 uint64_t reg_value = ReadRegisterUnsigned(*dwarf_reg, 0, &success);
2646 #if 0
2654 for r = 0 to regs-1
2657 for r = 0 to regs-1
2680 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2682 regs = Bits32(opcode, 7, 0) / 2;
2683 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2684 if (regs == 0 || regs > 16 || (d + regs) > 32)
2691 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2692 regs = Bits32(opcode, 7, 0);
2693 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
2694 if (regs == 0 || regs > 16 || (d + regs) > 32)
2710 for (i = 0; i < regs; ++i) {
2714 data = MemARead(context, addr, reg_byte_size, 0, &success);
2735 #if 0
2756 imm32 = Bits32(opcode, 7, 0);
2761 imm32 = Bits32(opcode, 23, 0);
2781 #if 0
2784 ITSTATE.IT<7:0> = firstcond:mask;
2787 m_it_session.InitIT(Bits32(opcode, 7, 0));
2800 #if 0
2822 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2827 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1);
2842 uint32_t imm11 = Bits32(opcode, 10, 0);
2855 uint32_t imm11 = Bits32(opcode, 10, 0);
2866 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2884 #if 0
2894 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
2917 if (m_ignore_conditions || (nonzero ^ (reg_val == 0)))
2938 #if 0
2959 Rm = Bits32(opcode, 3, 0);
2987 uint32_t offset = MemURead(context, addr, is_tbh ? 2 : 1, 0, &success) * 2;
3012 #if 0
3015 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3038 d = Bits32(opcode, 2, 0);
3051 imm32 = Bits32(opcode, 7, 0);
3083 uint32_t imm8 = Bits32(opcode, 7, 0);
3102 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3106 //(result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3107 AddWithCarryResult res = AddWithCarry(Rn, imm32, 0);
3133 #if 0
3137 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3172 AddWithCarryResult res = AddWithCarry(val1, imm32, 0);
3198 #if 0
3203 (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
3224 Rd = Bits32(opcode, 2, 0);
3229 shift_n = 0;
3232 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3236 shift_n = 0;
3245 Rm = Bits32(opcode, 3, 0);
3266 AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
3287 #if 0
3291 (result, carry, overflow) = AddWithCarry(R[n], imm32, '0');
3321 AddWithCarryResult res = AddWithCarry(reg_val, imm32, 0);
3334 #if 0
3339 (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
3354 Rn = Bits32(opcode, 2, 0);
3357 shift_n = 0;
3361 Rm = Bits32(opcode, 3, 0);
3369 Rm = Bits32(opcode, 3, 0);
3388 AddWithCarryResult res = AddWithCarry(val1, shifted, 0);
3400 #if 0
3418 imm32 = Bits32(opcode, 7, 0);
3451 #if 0
3471 Rn = Bits32(opcode, 2, 0);
3474 shift_n = 0;
3477 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3480 shift_n = 0;
3488 Rm = Bits32(opcode, 3, 0);
3495 Rm = Bits32(opcode, 3, 0);
3528 #if 0
3554 #if 0
3558 shift_n = UInt(R[m]<7:0>);
3576 #if 0
3601 #if 0
3605 shift_n = UInt(R[m]<7:0>);
3624 #if 0
3649 #if 0
3653 shift_n = UInt(R[m]<7:0>);
3672 #if 0
3698 #if 0
3702 shift_n = UInt(R[m]<7:0>);
3719 // In that case, bit [0] is shifted into the carry flag.
3722 #if 0
3771 Rd = Bits32(opcode, 2, 0);
3783 Rm = Bits32(opcode, 3, 0);
3791 Rm = Bits32(opcode, 3, 0);
3800 if (shift_type == SRType_ROR && imm5 == 0)
3846 Rd = Bits32(opcode, 2, 0);
3854 Rm = Bits32(opcode, 3, 0);
3861 Rn = Bits32(opcode, 3, 0);
3881 uint32_t amt = Bits32(val, 7, 0);
3903 #if 0
3909 for i = 0 to 14
3915 if wback && registers<n> == '0' then R[n] = R[n] + 4 * BitCount (registers);
3923 uint32_t registers = 0;
3929 // (registers<n> == '0');
3931 registers = Bits32(opcode, 7, 0);
3932 registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
3940 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
3942 registers = Bits32(opcode, 15, 0);
3943 registers = registers & 0xdfff; // Make sure bit 13 is zero.
3964 registers = Bits32(opcode, 15, 0);
3973 int32_t offset = 0;
3975 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
3985 for (int i = 0; i < 14; ++i) {
3997 0, &success);
4014 MemARead(context, base_address + offset, addr_byte_size, 0, &success);
4046 #if 0
4052 for i = 0 to 14
4059 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4067 uint32_t registers = 0;
4076 registers = Bits32(opcode, 15, 0);
4090 int32_t offset = 0;
4105 // for i = 0 to 14
4106 for (int i = 0; i < 14; ++i) {
4112 MemARead(context, address + offset, addr_byte_size, 0, &success);
4127 MemARead(context, address + offset, addr_byte_size, 0, &success);
4135 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4161 #if 0
4167 for i = 0 to 14
4173 if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4181 uint32_t registers = 0;
4186 // n = UInt(Rn); registers = P:M:'0':register_list; wback = (W == '1');
4188 registers = Bits32(opcode, 15, 0);
4189 registers = registers & 0xdfff; // Make sure bit 13 is a zero.
4212 registers = Bits32(opcode, 15, 0);
4227 int32_t offset = 0;
4229 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4241 for (int i = 0; i < 14; ++i) {
4246 MemARead(context, address + offset, addr_byte_size, 0, &success);
4263 MemARead(context, address + offset, addr_byte_size, 0, &success);
4271 // if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
4298 #if 0
4303 for i = 0 to 14
4309 if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
4317 uint32_t registers = 0;
4324 registers = Bits32(opcode, 15, 0);
4337 int32_t offset = 0;
4339 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4352 for (int i = 0; i < 14; ++i) {
4358 MemARead(context, address + offset, addr_byte_size, 0, &success);
4375 MemARead(context, address + offset, addr_byte_size, 0, &success);
4383 // if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
4408 #if 0
4418 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
4419 elsif UnalignedSupport() || address<1:0> = '00' then
4437 Rt = Bits32(opcode, 2, 0);
4451 imm32 = Bits32(opcode, 7, 0) << 2;
4465 imm32 = Bits32(opcode, 11, 0);
4480 // if P == '1' && U == '1' && W == '0' then SEE LDRT;
4481 // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 ==
4483 // if P == '0' && W == '0' then UNDEFINED;
4490 imm32 = Bits32(opcode, 7, 0);
4544 data = MemURead(context, address, 4, 0, &success);
4549 if (Bits32(address, 1, 0) == 0) {
4554 } else if (UnalignedSupport() || Bits32(address, 1, 0) == 0) {
4571 #if 0
4576 for i = 0 to 14
4593 uint32_t registers = 0;
4602 registers = Bits32(opcode, 7, 0);
4603 registers = registers & 0x00ff; // Make sure the top 8 bits are zeros.
4613 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4615 registers = Bits32(opcode, 15, 0);
4616 registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4632 registers = Bits32(opcode, 15, 0);
4646 int32_t offset = 0;
4648 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4657 // for i = 0 to 14
4659 for (uint32_t i = 0; i < 14; ++i) {
4672 0, &success);
4723 #if 0
4728 for i = 0 to 14
4746 uint32_t registers = 0;
4755 registers = Bits32(opcode, 15, 0);
4767 int32_t offset = 0;
4779 // for i = 0 to 14
4781 for (uint32_t i = 0; i < 14; ++i) {
4793 0, &success);
4845 #if 0
4850 for i = 0 to 14
4868 uint32_t registers = 0;
4879 // n = UInt(Rn); registers = '0':M:'0':register_list; wback = (W == '1');
4881 registers = Bits32(opcode, 15, 0);
4882 registers = registers & 0x5fff; // Make sure bits 15 & 13 are zeros.
4896 BitCount(Bits32(opcode, 15, 0)) >= 2) {
4901 registers = Bits32(opcode, 15, 0);
4914 int32_t offset = 0;
4916 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
4927 // for i = 0 to 14
4929 for (uint32_t i = 0; i < 14; ++i) {
4942 0, &success);
4994 #if 0
4999 for i = 0 to 14
5017 uint32_t registers = 0;
5026 registers = Bits32(opcode, 15, 0);
5038 int32_t offset = 0;
5051 // for i = 0 to 14
5052 for (uint32_t i = 0; i < 14; ++i) {
5065 0, &success);
5116 #if 0
5121 if UnalignedSupport() || address<1:0> == '00' then
5143 t = Bits32(opcode, 2, 0);
5157 imm32 = Bits32(opcode, 7, 0) << 2;
5173 imm32 = Bits32(opcode, 11, 0);
5186 // if P == '1' && U == '1' && W == '0' then SEE STRT;
5187 // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 ==
5189 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
5197 imm32 = Bits32(opcode, 7, 0);
5241 // if UnalignedSupport() || address<1:0> == '00' then
5243 (BitIsClear(address, 1) && BitIsClear(address, 0))) {
5246 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5283 #if 0
5293 if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() == InstrSet_ARM then
5320 t = Bits32(opcode, 2, 0);
5329 // (shift_t, shift_n) = (SRType_LSL, 0);
5331 shift_n = 0;
5342 m = Bits32(opcode, 3, 0);
5359 // if P == '0' && W == '1' then SEE STRT;
5363 m = Bits32(opcode, 3, 0);
5365 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
5392 int32_t offset = 0;
5395 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5400 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
5429 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5437 // if UnalignedSupport() || address<1:0> == '00' || CurrentInstrSet() ==
5440 (BitIsClear(address, 1) && BitIsClear(address, 0)) ||
5472 #if 0
5477 MemU[address,1] = R[t]<7:0>;
5494 t = Bits32(opcode, 2, 0);
5512 imm32 = Bits32(opcode, 11, 0);
5525 // if P == '1' && U == '1' && W == '0' then SEE STRBT;
5526 // if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
5533 imm32 = Bits32(opcode, 7, 0);
5552 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
5568 // MemU[address,1] = R[t]<7:0>
5580 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
5584 data = Bits32(data, 7, 0);
5605 // shifted left by 0, 1, 2, or 3 bits.
5608 #if 0
5614 if UnalignedSupport() || address<0> == '0' then
5615 MemU[address,2] = R[t]<15:0>;
5639 t = Bits32(opcode, 2, 0);
5648 // (shift_t, shift_n) = (SRType_LSL, 0);
5650 shift_n = 0;
5659 m = Bits32(opcode, 3, 0);
5679 // if P == '0' && W == '1' then SEE STRHT;
5683 m = Bits32(opcode, 3, 0);
5685 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
5691 // (shift_t, shift_n) = (SRType_LSL, 0);
5693 shift_n = 0;
5739 // if UnalignedSupport() || address<0> == '0' then
5740 if (UnalignedSupport() || BitIsClear(address, 0)) {
5741 // MemU[address,2] = R[t]<15:0>;
5757 if (!MemUWrite(context, address, Bits32(Rt, 15, 0), 2))
5782 #if 0
5851 #if 0
5877 Rd = Rn = Bits32(opcode, 2, 0);
5881 shift_n = 0;
5886 Rm = Bits32(opcode, 3, 0);
5895 Rm = Bits32(opcode, 3, 0);
5936 #if 0
5963 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB
5971 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB
5999 #if 0
6074 #if 0
6101 Rd = Rn = Bits32(opcode, 2, 0);
6105 shift_n = 0;
6110 Rm = Bits32(opcode, 3, 0);
6122 Rm = Bits32(opcode, 3, 0);
6164 #if 0
6239 #if 0
6266 Rd = Rn = Bits32(opcode, 2, 0);
6270 shift_n = 0;
6275 Rm = Bits32(opcode, 3, 0);
6284 Rm = Bits32(opcode, 3, 0);
6328 #if 0
6336 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6337 elsif UnalignedSupport() || address<1:0> = '00' then
6340 R[t] = ROR(data, 8*UInt(address<1:0>));
6358 // if P == '0' && W == '1' then SEE LDRT;
6359 // if Rn == '1101' && P == '0' && U == '1' && W == '0' && imm12 ==
6364 imm32 = Bits32(opcode, 11, 0);
6366 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
6408 uint64_t data = MemURead(context, address, addr_byte_size, 0, &success);
6423 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6424 if (BitIsClear(address, 1) && BitIsClear(address, 0)) {
6432 // elsif UnalignedSupport() || address<1:0> = '00' then
6434 (BitIsClear(address, 1) && BitIsClear(address, 0))) {
6444 // R[t] = ROR(data, 8*UInt(address<1:0>));
6445 data = ROR(data, Bits32(address, 1, 0), &success);
6464 #if 0
6473 if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6474 elsif UnalignedSupport() || address<1:0> = '00' then
6478 R[t] = ROR(data, 8*UInt(address<1:0>));
6502 t = Bits32(opcode, 2, 0);
6511 // (shift_t, shift_n) = (SRType_LSL, 0);
6513 shift_n = 0;
6522 m = Bits32(opcode, 3, 0);
6544 // if P == '0' && W == '1' then SEE LDRT;
6548 m = Bits32(opcode, 3, 0);
6550 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
6575 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
6580 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6613 uint64_t data = MemURead(context, address, addr_byte_size, 0, &success);
6628 // if address<1:0> == '00' then LoadWritePC(data); else UNPREDICTABLE;
6629 if (BitIsClear(address, 1) && BitIsClear(address, 0)) {
6636 // elsif UnalignedSupport() || address<1:0> = '00' then
6638 (BitIsClear(address, 1) && BitIsClear(address, 0))) {
6649 // R[t] = ROR(data, 8*UInt(address<1:0>));
6650 data = ROR(data, Bits32(address, 1, 0), &success);
6670 #if 0
6693 t = Bits32(opcode, 2, 0);
6708 imm32 = Bits32(opcode, 11, 0);
6730 // if P == '1' && U == '1' && W == '0' then SEE LDRBT;
6731 // if P == '0' && W == '0' then UNDEFINED;
6738 imm32 = Bits32(opcode, 7, 0);
6745 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD;
6764 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
6793 uint64_t data = MemURead(context, address, 1, 0, &success);
6817 #if 0
6835 imm32 = Bits32(opcode, 11, 0);
6851 imm32 = Bits32(opcode, 11, 0);
6882 uint64_t data = MemURead(context, address, 1, 0, &success);
6898 #if 0
6924 t = Bits32(opcode, 2, 0);
6933 // (shift_t, shift_n) = (SRType_LSL, 0);
6935 shift_n = 0;
6942 m = Bits32(opcode, 3, 0);
6967 // if P == '0' && W == '1' then SEE LDRBT;
6971 m = Bits32(opcode, 3, 0);
6973 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
7002 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7012 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7035 uint64_t data = MemURead(context, address, 1, 0, &success);
7060 #if 0
7067 if UnalignedSupport() || address<0> = '0' then
7086 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm5:'0', 32);
7087 t = Bits32(opcode, 2, 0);
7104 imm32 = Bits32(opcode, 11, 0);
7118 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE
7120 // if P == '1' && U == '1' && W == '0' then SEE LDRHT;
7121 // if P == '0' && W == '0' then UNDEFINED;
7128 imm32 = Bits32(opcode, 7, 0);
7146 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7172 uint64_t data = MemURead(context, address, 2, 0, &success);
7185 // if UnalignedSupport() || address<0> = '0' then
7186 if (UnalignedSupport() || BitIsClear(address, 0)) {
7207 #if 0
7213 if UnalignedSupport() || address<0> = '0' then
7232 imm32 = Bits32(opcode, 11, 0);
7243 uint32_t imm4L = Bits32(opcode, 3, 0);
7282 uint64_t data = MemURead(context, address, 2, 0, &success);
7286 // if UnalignedSupport() || address<0> = '0' then
7287 if (UnalignedSupport() || BitIsClear(address, 0)) {
7307 // register. The offset register value can be shifted left by 0, 1, 2, or 3
7311 #if 0
7319 if UnalignedSupport() || address<0> = '0' then
7343 t = Bits32(opcode, 2, 0);
7352 // (shift_t, shift_n) = (SRType_LSL, 0);
7354 shift_n = 0;
7364 m = Bits32(opcode, 3, 0);
7381 // if P == '0' && W == '1' then SEE LDRHT;
7385 m = Bits32(opcode, 3, 0);
7387 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
7393 // (shift_t, shift_n) = (SRType_LSL, 0);
7395 shift_n = 0;
7414 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7427 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7451 uint64_t data = MemURead(context, address, 2, 0, &success);
7464 // if UnalignedSupport() || address<0> = '0' then
7465 if (UnalignedSupport() || BitIsClear(address, 0)) {
7487 #if 0
7514 imm32 = Bits32(opcode, 11, 0);
7528 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLI;
7530 // if P == '1' && U == '1' && W == '0' then SEE LDRSBT;
7531 // if P == '0' && W == '0' then UNDEFINED;
7538 imm32 = Bits32(opcode, 7, 0);
7556 // if P == '0' && W == '1' then SEE LDRSBT;
7562 uint32_t imm4L = Bits32(opcode, 3, 0);
7565 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
7609 uint64_t unsigned_data = MemURead(context, address, 1, 0, &success);
7636 #if 0
7657 imm32 = Bits32(opcode, 11, 0);
7670 uint32_t imm4L = Bits32(opcode, 3, 0);
7706 uint64_t unsigned_data = MemURead(context, address, 1, 0, &success);
7721 // The offset register value can be shifted left by 0, 1, 2, or 3 bits.
7724 #if 0
7750 t = Bits32(opcode, 2, 0);
7759 // (shift_t, shift_n) = (SRType_LSL, 0);
7761 shift_n = 0;
7771 m = Bits32(opcode, 3, 0);
7788 // if P == '0' && W == '1' then SEE LDRSBT;
7792 m = Bits32(opcode, 3, 0);
7794 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
7800 // (shift_t, shift_n) = (SRType_LSL, 0);
7802 shift_n = 0;
7818 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
7832 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
7857 uint64_t unsigned_data = MemURead(context, address, 1, 0, &success);
7884 #if 0
7891 if UnalignedSupport() || address<0> = '0' then
7915 imm32 = Bits32(opcode, 11, 0);
7930 // if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE
7932 // if P == '1' && U == '1' && W == '0' then SEE LDRSHT;
7933 // if P == '0' && W == '0' then UNDEFINED;
7940 imm32 = Bits32(opcode, 7, 0);
7955 // if P == '0' && W == '1' then SEE LDRSHT;
7960 uint32_t imm4L = Bits32(opcode, 3, 0);
7963 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
7982 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
8007 uint64_t data = MemURead(context, address, 2, 0, &success);
8020 // if UnalignedSupport() || address<0> = '0' then
8021 if (UnalignedSupport() || BitIsClear(address, 0)) {
8043 #if 0
8049 if UnalignedSupport() || address<0> = '0' then
8068 imm32 = Bits32(opcode, 11, 0);
8081 uint32_t imm4L = Bits32(opcode, 3, 0);
8117 uint64_t data = MemURead(context, address, 2, 0, &success);
8121 // if UnalignedSupport() || address<0> = '0' then
8122 if (UnalignedSupport() || BitIsClear(address, 0)) {
8140 // register. The offset register value can be shifted left by 0, 1, 2, or 3
8144 #if 0
8152 if UnalignedSupport() || address<0> = '0' then
8176 t = Bits32(opcode, 2, 0);
8185 // (shift_t, shift_n) = (SRType_LSL, 0);
8187 shift_n = 0;
8197 m = Bits32(opcode, 3, 0);
8215 // if P == '0' && W == '1' then SEE LDRSHT;
8219 m = Bits32(opcode, 3, 0);
8221 // index = (P == '1'); add = (U == '1'); wback = (P == '0') ||
8227 // (shift_t, shift_n) = (SRType_LSL, 0);
8229 shift_n = 0;
8246 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8251 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
8285 uint64_t data = MemURead(context, address, 2, 0, &success);
8298 // if UnalignedSupport() || address<0> = '0' then
8299 if (UnalignedSupport() || BitIsClear(address, 0)) {
8319 // register. You can specifiy a rotation by 0, 8, 16, or 24 bits before
8323 #if 0
8327 R[d] = SignExtend(rotated<7:0>, 32);
8340 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8341 d = Bits32(opcode, 2, 0);
8343 rotation = 0;
8350 m = Bits32(opcode, 3, 0);
8362 m = Bits32(opcode, 3, 0);
8376 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8385 // R[d] = SignExtend(rotated<7:0>, 32);
8404 // register. You can specify a rotation by 0, 8, 16, or 24 bits before
8408 #if 0
8412 R[d] = SignExtend(rotated<15:0>, 32);
8425 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8426 d = Bits32(opcode, 2, 0);
8428 rotation = 0;
8435 m = Bits32(opcode, 3, 0);
8447 m = Bits32(opcode, 3, 0);
8461 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8470 // R[d] = SignExtend(rotated<15:0>, 32);
8489 // register. You can specify a rotation by 0, 8, 16, or 24 bits before
8493 #if 0
8497 R[d] = ZeroExtend(rotated<7:0>, 32);
8510 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8511 d = Bits32(opcode, 2, 0);
8513 rotation = 0;
8520 m = Bits32(opcode, 3, 0);
8532 m = Bits32(opcode, 3, 0);
8546 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8555 // R[d] = ZeroExtend(rotated<7:0>, 32);
8564 Bits32(rotated, 7, 0)))
8572 // register. You can specify a rotation by 0, 8, 16, or 24 bits before
8576 #if 0
8580 R[d] = ZeroExtend(rotated<15:0>, 32);
8592 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8593 d = Bits32(opcode, 2, 0);
8595 rotation = 0;
8602 m = Bits32(opcode, 3, 0);
8614 m = Bits32(opcode, 3, 0);
8628 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + m, 0, &success);
8637 // R[d] = ZeroExtend(rotated<15:0>, 32);
8646 Bits32(rotated, 15, 0)))
8657 #if 0
8741 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + n, 0, &success);
8764 uint64_t data = MemARead(context, address + 4, 4, 0, &success);
8771 uint64_t data2 = MemARead(context, address, 4, 0, &success);
8803 #if 0
8881 #if 0
8908 Rd = Rn = Bits32(opcode, 2, 0);
8912 shift_n = 0;
8917 Rm = Bits32(opcode, 3, 0);
8929 Rm = Bits32(opcode, 3, 0);
8972 #if 0
9048 #if 0
9075 Rd = Rn = Bits32(opcode, 2, 0);
9079 shift_n = 0;
9084 Rm = Bits32(opcode, 3, 0);
9096 Rm = Bits32(opcode, 3, 0);
9137 #if 0
9162 Rd = Bits32(opcode, 2, 0);
9165 imm32 = 0;
9209 #if 0
9238 Rm = Bits32(opcode, 3, 0);
9248 Rm = Bits32(opcode, 3, 0);
9288 #if 0
9347 #if 0
9376 Rm = Bits32(opcode, 3, 0);
9417 #if 0
9485 #if 0
9512 Rd = Rn = Bits32(opcode, 2, 0);
9516 shift_n = 0;
9521 Rm = Bits32(opcode, 3, 0);
9530 Rm = Bits32(opcode, 3, 0);
9569 #if 0
9591 Rd = Bits32(opcode, 2, 0);
9599 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
9615 // if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE;
9659 #if 0
9690 // if Rn == '1111' && S == '0' then SEE ADR;
9736 #if 0
9795 #if 0
9817 Rm = Bits32(opcode, 3, 0);
9824 Rm = Bits32(opcode, 3, 0);
9861 #if 0
9920 #if 0
9941 Rn = Bits32(opcode, 2, 0);
9944 shift_n = 0;
9948 Rm = Bits32(opcode, 3, 0);
9955 Rm = Bits32(opcode, 3, 0);
9990 #if 0
10019 m = Bits32(opcode, 3, 0);
10038 m = Bits32(opcode, 3, 0);
10088 #if 0
10091 shift_n = UInt(R[s]<7:0>);
10093 (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
10117 m = Bits32(opcode, 3, 0);
10133 // shift_n = UInt(R[s]<7:0>);
10138 uint32_t shift_n = Bits32(Rs, 7, 0);
10149 // (result, carry, overflow) = AddWithCarry(R[n], shifted, '0');
10154 AddWithCarryResult res = AddWithCarry(Rn, shifted, 0);
10184 #if 0
10213 d = Bits32(opcode, 2, 0);
10218 // (shift_t, shift_n) = (SRType_LSL, 0);
10220 shift_n = 0;
10228 m = Bits32(opcode, 3, 0);
10242 // if d == 13 || (d == 15 && S == '0') || n == 15 || BadReg(m) then
10255 m = Bits32(opcode, 3, 0);
10318 #if 0
10324 R[d] = 0;
10346 imm32 = Bits32(opcode, 7, 0) << 2;
10362 t = Bits32(opcode, 3, 0);
10364 imm32 = 0;
10403 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_r0 + t, 0, &success);
10410 // R[d] = 0;
10411 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + t, 0))
10414 #if 0 // unreachable because if true
10429 #if 0
10434 MemU[address,1] = R[t]<7:0>;
10450 // if P == '0' && W == '1' then SEE STRBT;
10454 imm32 = Bits32(opcode, 11, 0);
10456 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
10493 // MemU[address,1] = R[t]<7:0>;
10506 if (!MemUWrite(context, address, Bits32(Rt, 7, 0), 1))
10522 #if 0
10545 // if P == '0' && W == '1' then SEE STRT;
10546 // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm12 ==
10551 imm32 = Bits32(opcode, 11, 0);
10553 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
10631 #if 0
10654 // if P == '0' && W == '0' then SEE 'Related encodings';
10661 imm32 = Bits32(opcode, 7, 0) << 2;
10680 // if Rt<0> == '1' then UNPREDICTABLE;
10684 if (BitIsSet(t, 0))
10688 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0);
10690 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
10695 // if P == '0' && W == '1' then UNPREDICTABLE;
10741 uint32_t data = MemARead(context, address, addr_byte_size, 0, &success);
10750 data = MemARead(context, address + 4, addr_byte_size, 0, &success);
10777 #if 0
10800 // if Rt<0> == '1' then UNPREDICTABLE;
10803 if (BitIsSet(t, 0))
10807 m = Bits32(opcode, 3, 0);
10809 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
10814 // if P == '0' && W == '1' then UNPREDICTABLE;
10866 uint32_t data = MemARead(context, address, addr_byte_size, 0, &success);
10875 data = MemARead(context, address + 4, addr_byte_size, 0, &success);
10902 #if 0
10925 // if P == '0' && W == '0' then SEE 'Related encodings';
10931 imm32 = Bits32(opcode, 7, 0) << 2;
10949 // if Rt<0> == '1' then UNPREDICTABLE;
10953 if (BitIsSet(t, 0))
10958 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0);
10960 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
10965 // if P == '0' && W == '1' then UNPREDICTABLE;
11055 #if 0
11078 // if Rt<0> == '1' then UNPREDICTABLE;
11081 if (BitIsSet(t, 0))
11086 m = Bits32(opcode, 3, 0);
11088 // index = (P == '1'); add = (U == '1'); wback = (P == '0') || (W == '1');
11093 // if P == '0' && W == '1' then UNPREDICTABLE;
11192 #if 0
11197 for r = 0 to regs-1
11221 // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings';
11222 // if P == '0' && U == '1' && W == '1' && Rn == '1101' then SEE VPOP;
11223 // if P == '1' && W == '0' then SEE VLDR;
11238 imm32 = Bits32(opcode, 7, 0) << 2;
11241 regs = Bits32(opcode, 7, 0) / 2;
11248 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
11249 if ((regs == 0) || (regs > 16) || ((d + regs) > 32))
11256 // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings';
11257 // if P == '0' && U == '1' && W == '1' && Rn == '1101' then SEE VPOP;
11258 // if P == '1' && W == '0' then SEE VLDR;
11274 imm32 = Bits32(opcode, 7, 0) << 2;
11275 regs = Bits32(opcode, 7, 0);
11282 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
11283 if ((regs == 0) || ((d + regs) > 32))
11327 // for r = 0 to regs-1
11328 for (uint32_t r = 0; r < regs; ++r) {
11333 uint32_t data = MemARead(context, address, addr_byte_size, 0, &success);
11347 MemARead(context, address, addr_byte_size, 0, &success);
11353 MemARead(context, address + 4, addr_byte_size, 0, &success);
11385 #if 0
11390 for r = 0 to regs-1
11396 MemA[address,4] = if BigEndian() then D[d+r]<63:32> else D[d+r]<31:0>;
11397 MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else D[d+r]<63:32>;
11415 // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings';
11416 // if P == '1' && U == '0' && W == '1' && Rn == '1101' then SEE VPUSH;
11417 // if P == '1' && W == '0' then SEE VSTR;
11432 imm32 = Bits32(opcode, 7, 0) << 2;
11435 regs = Bits32(opcode, 7, 0) / 2;
11442 // if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
11443 if ((regs == 0) || (regs > 16) || ((d + regs) > 32))
11450 // if P == '0' && U == '0' && W == '0' then SEE 'Related encodings';
11451 // if P == '1' && U == '0' && W == '1' && Rn == '1101' then SEE VPUSH;
11452 // if P == '1' && W == '0' then SEE VSTR;
11468 imm32 = Bits32(opcode, 7, 0) << 2;
11469 regs = Bits32(opcode, 7, 0);
11476 // if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;
11477 if ((regs == 0) || ((d + regs) > 32))
11521 // for r = 0 to regs-1
11522 for (uint32_t r = 0; r < regs; ++r) {
11527 start_reg + d + r, 0, &success);
11542 // D[d+r]<31:0>;
11543 // MemA[address+4,4] = if BigEndian() then D[d+r]<31:0> else
11546 start_reg + d + r, 0, &success);
11562 if (!MemAWrite(context, address + 4, Bits64(data, 31, 0),
11568 if (!MemAWrite(context, address, Bits64(data, 31, 0), addr_byte_size))
11590 #if 0
11620 imm32 = Bits32(opcode, 7, 0) << 2;
11633 imm32 = Bits32(opcode, 7, 0) << 2;
11674 uint32_t data = MemARead(context, address, addr_byte_size, 0, &success);
11683 uint32_t word1 = MemARead(context, address, addr_byte_size, 0, &success);
11689 MemARead(context, address + 4, addr_byte_size, 0, &success);
11717 #if 0
11726 MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11727 MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11746 imm32 = Bits32(opcode, 7, 0) << 2;
11763 imm32 = Bits32(opcode, 7, 0) << 2;
11804 ReadRegisterUnsigned(eRegisterKindDWARF, start_reg + d, 0, &success);
11813 // MemA[address,4] = if BigEndian() then D[d]<63:32> else D[d]<31:0>;
11814 // MemA[address+4,4] = if BigEndian() then D[d]<31:0> else D[d]<63:32>;
11816 ReadRegisterUnsigned(eRegisterKindDWARF, start_reg + d, 0, &success);
11826 if (!MemAWrite(context, address + 4, Bits64(data, 31, 0),
11830 if (!MemAWrite(context, address, Bits64(data, 31, 0), addr_byte_size))
11849 #if 0
11852 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
11854 for r = 0 to regs-1
11855 for e = 0 to elements-1
11913 if (align == 0)
11926 m = Bits32(opcode, 3, 0);
11948 // address = R[n]; if (address MOD alignment) != 0 then
11951 if ((address % alignment) != 0)
11976 // for r = 0 to regs-1
11977 for (uint32_t r = 0; r < regs; ++r) {
11978 // for e = 0 to elements-1
11979 uint64_t assembled_data = 0;
11980 for (uint32_t e = 0; e < elements; ++e) {
11984 uint64_t data = MemURead(context, address, ebytes, 0, &success);
12007 #if 0
12010 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12037 if (size == 0) // when '00'
12039 // if index_align<0> != '0' then UNDEFINED;
12040 if (BitIsClear(index_align, 0))
12050 // if index_align<1> != '0' then UNDEFINED;
12059 // alignment = if index_align<0> == '0' then 1 else 2;
12060 if (BitIsClear(index_align, 0))
12066 // if index_align<2> != '0' then UNDEFINED;
12070 // if index_align<1:0> != '00' && index_align<1:0> != '11' then
12072 if ((Bits32(index_align, 1, 0) != 0) &&
12073 (Bits32(index_align, 1, 0) != 3))
12081 // alignment = if index_align<1:0> == '00' then 1 else 4;
12082 if (Bits32(index_align, 1, 0) == 0)
12092 m = Bits32(opcode, 3, 0);
12112 // address = R[n]; if (address MOD alignment) != 0 then
12115 if ((address % alignment) != 0)
12144 uint32_t element = MemURead(context, address, esize, 0, &success);
12151 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_d0 + d, 0, &success);
12158 // where 'element' goes, & all 0's
12160 if (index > 0)
12162 0); // add 1's to the right of where 'element' goes.
12163 // now mask should be 0's where element goes & 1's everywhere else.
12183 #if 0
12186 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12188 for r = 0 to regs-1
12189 for e = 0 to elements-1
12241 if (align == 0)
12254 m = Bits32(opcode, 3, 0);
12280 // address = R[n]; if (address MOD alignment) != 0 then
12283 if ((address % alignment) != 0)
12308 // for r = 0 to regs-1
12309 for (uint32_t r = 0; r < regs; ++r) {
12313 eRegisterKindDWARF, dwarf_d0 + d + r, 0, &success);
12317 // for e = 0 to elements-1
12318 for (uint32_t e = 0; e < elements; ++e) {
12339 #if 0
12342 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12371 if (size == 0) // when '00'
12373 // if index_align<0> != '0' then UNDEFINED;
12374 if (BitIsClear(index_align, 0))
12383 // if index_align<1> != '0' then UNDEFINED;
12392 // alignment = if index_align<0> == '0' then 1 else 2;
12393 if (BitIsClear(index_align, 0))
12399 // if index_align<2> != '0' then UNDEFINED;
12403 // if index_align<1:0> != '00' && index_align<1:0> != '11' then
12405 if ((Bits32(index_align, 1, 0) != 0) &&
12406 (Bits32(index_align, 1, 0) != 3))
12414 // alignment = if index_align<1:0> == '00' then 1 else 4;
12415 if (Bits32(index_align, 1, 0) == 0)
12425 m = Bits32(opcode, 3, 0);
12447 // address = R[n]; if (address MOD alignment) != 0 then
12450 if ((address % alignment) != 0)
12476 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_d0 + d, 0, &success);
12498 #if 0
12501 address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
12504 for r = 0 to regs-1
12526 if ((size == 3) || ((size == 0) && BitIsSet(opcode, 4)))
12529 // ebytes = 1 << UInt(size); elements = 8 DIV ebytes; regs = if T == '0'
12538 // alignment = if a == '0' then 1 else ebytes;
12547 m = Bits32(opcode, 3, 0);
12569 // address = R[n]; if (address MOD alignment) != 0 then
12572 if ((address % alignment) != 0)
12601 uint64_t word = MemURead(context, address, ebytes, 0, &success);
12605 uint64_t replicated_element = 0;
12607 for (uint32_t e = 0; e < elements; ++e)
12609 (replicated_element << esize) | Bits64(word, esize - 1, 0);
12611 // for r = 0 to regs-1
12612 for (uint32_t r = 0; r < regs; ++r) {
12628 #if 0
12639 when '0100' (result, -, -) = AddWithCarry(R[n], operand2, '0'); // ADD
12668 imm32 = Bits32(opcode, 7, 0);
12690 m = Bits32(opcode, 3, 0);
12725 case 0: // when '0000'
12746 // (result, -, -) = AddWithCarry(R[n], operand2, '0'); // ADD
12747 result = AddWithCarry(Rn, operand2, 0);
12793 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_cpsr, 0, &success);
12816 {0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12818 {0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, No_VFP, eSize32,
12822 {0x0ffff000, 0x028d7000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12824 {0x0ffff000, 0x024c7000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12827 {0x0fffffff, 0x01a0c00d, ARMvAll, eEncodingA1, No_VFP, eSize32,
12829 {0x0ffff000, 0x028dc000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12831 {0x0ffff000, 0x024dc000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12835 {0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12837 {0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12843 {0x0e5f0000, 0x040d0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12847 {0x0fbf0f00, 0x0d2d0b00, ARMV6T2_ABOVE, eEncodingA1, No_VFP, eSize32,
12849 {0x0fbf0f00, 0x0d2d0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32,
12854 {0x0fff0000, 0x08bd0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12856 {0x0fff0fff, 0x049d0004, ARMvAll, eEncodingA2, No_VFP, eSize32,
12858 {0x0fbf0f00, 0x0cbd0b00, ARMV6T2_ABOVE, eEncodingA1, No_VFP, eSize32,
12860 {0x0fbf0f00, 0x0cbd0a00, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32,
12864 {0x0f000000, 0x0f000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12870 {0xfe000000, 0xfa000000, ARMV5_ABOVE, eEncodingA2, No_VFP, eSize32,
12872 {0x0f000000, 0x0a000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12874 {0x0f000000, 0x0b000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12876 {0x0ffffff0, 0x012fff30, ARMV5_ABOVE, eEncodingA1, No_VFP, eSize32,
12879 {0x0ffffff0, 0x012fff10, ARMvAll, eEncodingA1, No_VFP, eSize32,
12882 {0x0ffffff0, 0x012fff20, ARMvAll, eEncodingA1, No_VFP, eSize32,
12887 {0x0fe00000, 0x02a00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12890 {0x0fe00010, 0x00a00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12894 {0x0fe00000, 0x02800000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12898 {0x0fe00010, 0x00800000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12902 {0x0fe00090, 0x00800010, ARMvAll, eEncodingA1, No_VFP, eSize32,
12906 {0x0fff0000, 0x028f0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12908 {0x0fff0000, 0x024f0000, ARMvAll, eEncodingA2, No_VFP, eSize32,
12911 {0x0fe00000, 0x02000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12914 {0x0fe00010, 0x00000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12918 {0x0fe00000, 0x03c00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12921 {0x0fe00010, 0x01c00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12925 {0x0fe00000, 0x02200000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12928 {0x0fe00010, 0x00200000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12932 {0x0fe00000, 0x03800000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12935 {0x0fe00010, 0x01800000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12939 {0x0fe00000, 0x02600000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12942 {0x0fe00010, 0x00600000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12946 {0x0fe00000, 0x02e00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12949 {0x0fe00010, 0x00e00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12953 {0x0fe00000, 0x02c00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12956 {0x0fe00010, 0x00c00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12960 {0x0fe00000, 0x02400000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12964 {0x0fef0000, 0x024d0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12967 {0x0fe00010, 0x00400000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12971 {0x0ff0f000, 0x03300000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12974 {0x0ff0f010, 0x01300000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12977 {0x0ff0f000, 0x03100000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12980 {0x0ff0f010, 0x01100000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12984 {0x0fef0000, 0x03a00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12986 {0x0ff00000, 0x03000000, ARMV6T2_ABOVE, eEncodingA2, No_VFP, eSize32,
12989 {0x0fef0ff0, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12992 {0x0fef0000, 0x03e00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12995 {0x0fef0010, 0x01e00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
12999 {0x0ff0f000, 0x03700000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13002 {0x0ff0f010, 0x01700000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13005 {0x0ff0f000, 0x03500000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13008 {0x0ff0f010, 0x01500000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13011 {0x0fef0070, 0x01a00040, ARMvAll, eEncodingA1, No_VFP, eSize32,
13014 {0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32,
13017 {0x0fef0070, 0x01a00000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13020 {0x0fef00f0, 0x01a00010, ARMvAll, eEncodingA1, No_VFP, eSize32,
13023 {0x0fef0070, 0x01a00020, ARMvAll, eEncodingA1, No_VFP, eSize32,
13026 {0x0fef00f0, 0x01a00050, ARMvAll, eEncodingA1, No_VFP, eSize32,
13029 {0x0fef0ff0, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32,
13032 {0x0fef0070, 0x01a00060, ARMvAll, eEncodingA1, No_VFP, eSize32,
13035 {0x0fef00f0, 0x01a00070, ARMvAll, eEncodingA1, No_VFP, eSize32,
13038 {0x0fe000f0, 0x00000090, ARMvAll, eEncodingA1, No_VFP, eSize32,
13042 {0x0e10f000, 0x0210f000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13045 {0x0e10f010, 0x0010f000, ARMvAll, eEncodingA2, No_VFP, eSize32,
13050 {0x0fd00000, 0x08900000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13052 {0x0fd00000, 0x08100000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13054 {0x0fd00000, 0x09100000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13056 {0x0fd00000, 0x09900000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13058 {0x0e500000, 0x04100000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13061 {0x0e500010, 0x06100000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13064 {0x0e5f0000, 0x045f0000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13066 {0xfe500010, 0x06500000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13069 {0x0e5f00f0, 0x005f00b0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13071 {0x0e5000f0, 0x001000b0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13074 {0x0e5000f0, 0x005000d0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13077 {0x0e5f00f0, 0x005f00d0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13079 {0x0e5000f0, 0x001000d0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13082 {0x0e5000f0, 0x005000f0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13085 {0x0e5f00f0, 0x005f00f0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13087 {0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13090 {0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32,
13093 {0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32,
13096 {0x0e100f00, 0x0c100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32,
13098 {0x0e100f00, 0x0c100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32,
13100 {0x0f300f00, 0x0d100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32,
13102 {0x0f300f00, 0x0d100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32,
13104 {0xffb00000, 0xf4200000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32,
13107 {0xffb00300, 0xf4a00000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32,
13110 {0xffb00f00, 0xf4a00c00, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32,
13115 {0x0fd00000, 0x08800000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13117 {0x0fd00000, 0x08000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13119 {0x0fd00000, 0x09000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13121 {0x0fd00000, 0x09800000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13123 {0x0e500010, 0x06000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13126 {0x0e5000f0, 0x000000b0, ARMvAll, eEncodingA1, No_VFP, eSize32,
13129 {0x0ff00ff0, 0x01800f90, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
13131 {0x0e500000, 0x04400000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13134 {0x0e500000, 0x04000000, ARMvAll, eEncodingA1, No_VFP, eSize32,
13137 {0x0e5000f0, 0x004000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32,
13140 {0x0e500ff0, 0x000000f0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32,
13143 {0x0e100f00, 0x0c000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32,
13145 {0x0e100f00, 0x0c000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32,
13147 {0x0f300f00, 0x0d000b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32,
13149 {0x0f300f00, 0x0d000a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32,
13151 {0xffb00000, 0xf4000000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32,
13154 {0xffb00300, 0xf4800000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32,
13159 {0x0fff00f0, 0x06af00f0, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
13161 {0x0fff00f0, 0x06bf0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
13163 {0x0fff00f0, 0x06ef0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
13165 {0x0fff00f0, 0x06ff0070, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
13167 {0xfe500000, 0xf8100000, ARMV6_ABOVE, eEncodingA1, No_VFP, eSize32,
13173 for (size_t i = 0; i < k_num_arm_opcodes; ++i) {
13175 (g_arm_opcodes[i].variants & arm_isa) != 0)
13189 {0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, No_VFP, eSize16,
13191 {0xffff0000, 0xe92d0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13193 {0xffff0fff, 0xf84d0d04, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13197 {0xffffff00, 0x0000af00, ARMvAll, eEncodingT1, No_VFP, eSize16,
13200 {0xffffffff, 0x0000466f, ARMvAll, eEncodingT1, No_VFP, eSize16,
13204 {0xffffffc0, 0x00004640, ARMvAll, eEncodingT1, No_VFP, eSize16,
13208 {0xfffff800, 0x00004800, ARMvAll, eEncodingT1, No_VFP, eSize16,
13212 {0xffffff87, 0x00004485, ARMvAll, eEncodingT2, No_VFP, eSize16,
13214 {0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, No_VFP, eSize16,
13216 {0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13218 {0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13220 {0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13225 {0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13227 {0xffbf0f00, 0xed2d0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13232 {0xfffff800, 0x0000a800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13234 {0xffffff80, 0x0000b000, ARMvAll, eEncodingT2, No_VFP, eSize16,
13236 {0xfffffe00, 0x0000bc00, ARMvAll, eEncodingT1, No_VFP, eSize16,
13238 {0xffff0000, 0xe8bd0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13240 {0xffff0fff, 0xf85d0d04, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13242 {0xffbf0f00, 0xecbd0b00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13244 {0xffbf0f00, 0xecbd0a00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13248 {0xffffff00, 0x0000df00, ARMvAll, eEncodingT1, No_VFP, eSize16,
13253 {0xffffffff, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16,
13255 {0xffffffff, 0x0000bf10, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16,
13257 {0xffffffff, 0x0000bf20, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16,
13259 {0xffffffff, 0x0000bf30, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16,
13261 {0xffffffff, 0x0000bf40, ARMV7_ABOVE, eEncodingT1, No_VFP, eSize16,
13263 {0xffffff00, 0x0000bf00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16,
13268 {0xfffff000, 0x0000d000, ARMvAll, eEncodingT1, No_VFP, eSize16,
13270 {0xfffff800, 0x0000e000, ARMvAll, eEncodingT2, No_VFP, eSize16,
13272 {0xf800d000, 0xf0008000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13274 {0xf800d000, 0xf0009000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32,
13278 {0xf800d000, 0xf000d000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize32,
13281 {0xf800d001, 0xf000c000, ARMV5_ABOVE, eEncodingT2, No_VFP, eSize32,
13283 {0xffffff87, 0x00004780, ARMV5_ABOVE, eEncodingT1, No_VFP, eSize16,
13286 {0xffffff87, 0x00004700, ARMvAll, eEncodingT1, No_VFP, eSize32,
13289 {0xfff0ffff, 0xf3c08f00, ARMV5J_ABOVE, eEncodingT1, No_VFP, eSize32,
13292 {0xfffff500, 0x0000b100, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16,
13295 {0xfff0fff0, 0xe8d0f000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13298 {0xfff0fff0, 0xe8d0f010, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13303 {0xfbe08000, 0xf1400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13306 {0xffffffc0, 0x00004140, ARMvAll, eEncodingT1, No_VFP, eSize16,
13308 {0xffe08000, 0xeb400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13312 {0xfffffe00, 0x00001800, ARMvAll, eEncodingT1, No_VFP, eSize16,
13316 {0xffffff00, 0x00004400, ARMvAll, eEncodingT2, No_VFP, eSize16,
13319 {0xfffff800, 0x0000a000, ARMvAll, eEncodingT1, No_VFP, eSize16,
13321 {0xfbff8000, 0xf2af0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13323 {0xfbff8000, 0xf20f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13326 {0xfbe08000, 0xf0000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13329 {0xffffffc0, 0x00004000, ARMvAll, eEncodingT1, No_VFP, eSize16,
13331 {0xffe08000, 0xea000000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13335 {0xfbe08000, 0xf0200000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13338 {0xffffffc0, 0x00004380, ARMvAll, eEncodingT1, No_VFP, eSize16,
13340 {0xffe08000, 0xea200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13344 {0xfbe08000, 0xf0800000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13347 {0xffffffc0, 0x00004040, ARMvAll, eEncodingT1, No_VFP, eSize16,
13349 {0xffe08000, 0xea800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13353 {0xfbe08000, 0xf0400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13356 {0xffffffc0, 0x00004300, ARMvAll, eEncodingT1, No_VFP, eSize16,
13358 {0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13362 {0xffffffc0, 0x00004240, ARMvAll, eEncodingT1, No_VFP, eSize16,
13363 &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
13364 {0xfbe08000, 0xf1c00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13368 {0xffe08000, 0xea400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13372 {0xfbe08000, 0xf1600000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13375 {0xffffffc0, 0x00004180, ARMvAll, eEncodingT1, No_VFP, eSize16,
13377 {0xffe08000, 0xeb600000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13381 {0xfffffe00, 0x00001c00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13384 {0xfffff800, 0x00003000, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16,
13386 {0xfbe08000, 0xf1000000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13389 {0xfbf08000, 0xf2000000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32,
13393 {0xfffffe00, 0x00001e00, ARMvAll, eEncodingT1, No_VFP, eSize16,
13396 {0xfffff800, 0x00003800, ARMvAll, eEncodingT2, No_VFP, eSize16,
13398 {0xfbe08000, 0xf1a00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13401 {0xfbf08000, 0xf2a00000, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32,
13405 {0xfbef8000, 0xf1ad0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13407 {0xfbff8000, 0xf2ad0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13410 {0xfffffe00, 0x00001a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13412 {0xffe08000, 0xeba00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13416 {0xfbf08f00, 0xf0900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13419 {0xfff08f00, 0xea900f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13422 {0xfbf08f00, 0xf0100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13425 {0xffffffc0, 0x00004200, ARMvAll, eEncodingT1, No_VFP, eSize16,
13427 {0xfff08f00, 0xea100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13431 {0xffffff00, 0x00004600, ARMvAll, eEncodingT1, No_VFP, eSize16,
13434 {0xffffffc0, 0x00000000, ARMvAll, eEncodingT2, No_VFP, eSize16,
13437 {0xffeff0f0, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13440 {0xfffff800, 0x00002000, ARMvAll, eEncodingT1, No_VFP, eSize16,
13442 {0xfbef8000, 0xf04f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13444 {0xfbf08000, 0xf2400000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13447 {0xfbef8000, 0xf06f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13450 {0xffffffc0, 0x000043c0, ARMvAll, eEncodingT1, No_VFP, eSize16,
13452 {0xffef8000, 0xea6f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13456 {0xfbf08f00, 0xf1100f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13459 {0xffffffc0, 0x000042c0, ARMvAll, eEncodingT1, No_VFP, eSize16,
13461 {0xfff08f00, 0xeb100f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13464 {0xfffff800, 0x00002800, ARMvAll, eEncodingT1, No_VFP, eSize16,
13466 {0xfbf08f00, 0xf1b00f00, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13469 {0xffffffc0, 0x00004280, ARMvAll, eEncodingT1, No_VFP, eSize16,
13472 {0xffffff00, 0x00004500, ARMvAll, eEncodingT2, No_VFP, eSize16,
13474 {0xfff08f00, 0xebb00f00, ARMvAll, eEncodingT3, No_VFP, eSize16,
13478 {0xfffff800, 0x00001000, ARMvAll, eEncodingT1, No_VFP, eSize16,
13480 {0xffef8030, 0xea4f0020, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13483 {0xffffffc0, 0x00004100, ARMvAll, eEncodingT1, No_VFP, eSize16,
13485 {0xffe0f0f0, 0xfa40f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13488 {0xfffff800, 0x00000000, ARMvAll, eEncodingT1, No_VFP, eSize16,
13490 {0xffef8030, 0xea4f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13493 {0xffffffc0, 0x00004080, ARMvAll, eEncodingT1, No_VFP, eSize16,
13495 {0xffe0f0f0, 0xfa00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13498 {0xfffff800, 0x00000800, ARMvAll, eEncodingT1, No_VFP, eSize16,
13500 {0xffef8030, 0xea4f0010, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13503 {0xffffffc0, 0x000040c0, ARMvAll, eEncodingT1, No_VFP, eSize16,
13505 {0xffe0f0f0, 0xfa20f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13508 {0xffeff0f0, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13511 {0xffef8030, 0xea4f0030, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13514 {0xffffffc0, 0x000041c0, ARMvAll, eEncodingT1, No_VFP, eSize16,
13516 {0xffe0f0f0, 0xfa60f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13519 {0xffffffc0, 0x00004340, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13522 {0xfff0f0f0, 0xfb00f000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13526 {0xffffff00, 0xf3de8f00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13533 {0xffd0ffff, 0xe810c000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13535 {0xffd0ffff, 0xe990c000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13539 {0xfffff800, 0x0000c800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13541 {0xffd02000, 0xe8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13543 {0xffd00000, 0xe9100000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13545 {0xfffff800, 0x00006800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13547 {0xfffff800, 0x00009800, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16,
13549 {0xfff00000, 0xf8d00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13552 {0xfff00800, 0xf8500800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32,
13556 {0xff7f0000, 0xf85f0000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13559 {0xfffffe00, 0x00005800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13561 {0xfff00fc0, 0xf8500000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13564 {0xfffff800, 0x00007800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13567 {0xfff00000, 0xf8900000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13570 {0xfff00800, 0xf8100800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13573 {0xff7f0000, 0xf81f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13575 {0xfffffe00, 0x00005c00, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize16,
13577 {0xfff00fc0, 0xf8100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13580 {0xfffff800, 0x00008800, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13583 {0xfff00000, 0xf8b00000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13586 {0xfff00800, 0xf8300800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13589 {0xff7f0000, 0xf83f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13591 {0xfffffe00, 0x00005a00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13594 {0xfff00fc0, 0xf8300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13597 {0xfff00000, 0xf9900000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13600 {0xfff00800, 0xf9100800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13603 {0xff7f0000, 0xf91f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13605 {0xfffffe00, 0x00005600, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13608 {0xfff00fc0, 0xf9100000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13611 {0xfff00000, 0xf9b00000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13614 {0xfff00800, 0xf9300800, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13617 {0xff7f0000, 0xf93f0000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13619 {0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13622 {0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13625 {0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13628 {0xfe100f00, 0xec100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32,
13630 {0xfe100f00, 0xec100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32,
13632 {0xffe00f00, 0xed100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32,
13634 {0xff300f00, 0xed100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32,
13636 {0xffb00000, 0xf9200000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32,
13639 {0xffb00300, 0xf9a00000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32,
13642 {0xffb00f00, 0xf9a00c00, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32,
13647 {0xfffff800, 0x0000c000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13649 {0xffd00000, 0xe8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13651 {0xffd00000, 0xe9000000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13653 {0xfffff800, 0x00006000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13655 {0xfffff800, 0x00009000, ARMV4T_ABOVE, eEncodingT2, No_VFP, eSize16,
13657 {0xfff00000, 0xf8c00000, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13660 {0xfff00800, 0xf8400800, ARMV6T2_ABOVE, eEncodingT4, No_VFP, eSize32,
13663 {0xfffffe00, 0x00005000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13665 {0xfff00fc0, 0xf8400000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13668 {0xfffff800, 0x00007000, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13671 {0xfff00000, 0xf8800000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13674 {0xfff00800, 0xf8000800, ARMV6T2_ABOVE, eEncodingT3, No_VFP, eSize32,
13677 {0xfffffe00, 0x00005200, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16,
13679 {0xfff00fc0, 0xf8200000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13682 {0xfff00000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13685 {0xfe500000, 0xe8400000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32,
13688 {0xfe100f00, 0xec000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32,
13690 {0xfea00f00, 0xec000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32,
13692 {0xff300f00, 0xed000b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32,
13694 {0xff300f00, 0xed000a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32,
13696 {0xffb00000, 0xf9000000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32,
13699 {0xffb00300, 0xf9800000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32,
13704 {0xffffffc0, 0x0000b240, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16,
13706 {0xfffff080, 0xfa4ff080, ARMV6_ABOVE, eEncodingT2, No_VFP, eSize32,
13708 {0xffffffc0, 0x0000b200, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16,
13710 {0xfffff080, 0xfa0ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13712 {0xffffffc0, 0x0000b2c0, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16,
13714 {0xfffff080, 0xfa5ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13716 {0xffffffc0, 0x0000b280, ARMV6_ABOVE, eEncodingT1, No_VFP, eSize16,
13718 {0xfffff080, 0xfa1ff080, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32,
13723 for (size_t i = 0; i < k_num_thumb_opcodes; ++i) {
13725 (g_thumb_opcodes[i].variants & arm_isa) != 0)
13733 m_arm_isa = 0;
13761 return m_arm_isa != 0;
13794 LLDB_REGNUM_GENERIC_FLAGS, 0, &success);
13806 uint32_t thumb_opcode = MemARead(read_inst_context, pc, 2, 0, &success);
13809 if ((thumb_opcode & 0xe000) != 0xe000 ||
13810 ((thumb_opcode & 0x1800u) == 0)) {
13815 MemARead(read_inst_context, pc + 2, 2, 0, &success),
13821 m_opcode.SetOpcode32(MemARead(read_inst_context, pc, 4, 0, &success),
13830 if (it != 0)
13857 case 0:
13858 if (m_opcode_cpsr == 0)
13861 result = (m_opcode_cpsr & MASK_CPSR_Z) != 0;
13864 if (m_opcode_cpsr == 0)
13867 result = (m_opcode_cpsr & MASK_CPSR_C) != 0;
13870 if (m_opcode_cpsr == 0)
13873 result = (m_opcode_cpsr & MASK_CPSR_N) != 0;
13876 if (m_opcode_cpsr == 0)
13879 result = (m_opcode_cpsr & MASK_CPSR_V) != 0;
13882 if (m_opcode_cpsr == 0)
13885 result = ((m_opcode_cpsr & MASK_CPSR_C) != 0) &&
13886 ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
13889 if (m_opcode_cpsr == 0)
13898 if (m_opcode_cpsr == 0)
13903 result = n == v && ((m_opcode_cpsr & MASK_CPSR_Z) == 0);
13907 // Always execute (cond == 0b1110, or the special 0b1111 which gives
13931 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 8) != 0x0f)
13934 if (Bits32(opcode, 31, 27) == 0x1e && Bits32(opcode, 15, 14) == 0x02 &&
13935 Bits32(opcode, 12, 12) == 0x00 && Bits32(opcode, 25, 22) <= 0x0d) {
13982 uint32_t mode = Bits32(m_opcode_cpsr, 4, 0);
14017 if (BitIsSet(bytemask, 0)) {
14023 tmp_cpsr = tmp_cpsr | Bits32(value, 4, 0);
14035 target = addr & 0xfffffffc;
14037 target = addr & 0xfffffffe;
14052 if (BitIsSet(addr, 0)) {
14057 target = addr & 0xfffffffe;
14064 target = addr & 0xfffffffc;
14067 return false; // address<1:0> == '10' => UNPREDICTABLE
14140 result = UnsignedBits(unsigned_sum, 31, 0);
14141 // carry_out = (result == unsigned_sum ? 0 : 1);
14142 overflow = ((int32_t)result == signed_sum ? 0 : 1);
14145 carry_out = ((int32_t)x >= (int32_t)(~y)) ? 1 : 0;
14147 carry_out = ((int32_t)x > (int32_t)y) ? 1 : 0;
14174 // assert(0 && "Invalid register number");
14182 uint32_t val = ReadRegisterUnsigned(reg_kind, reg_num, 0, success);
14214 // defaults to ~0u.
14260 SetBit32(m_new_inst_cpsr, CPSR_Z_POS, result == 0 ? 1 : 0);
14261 if (carry != ~0u)
14263 if (overflow != ~0u)
14288 if (m_opcode_cpsr == 0 || !m_ignore_conditions) {
14290 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_cpsr, 0, &success);
14298 uint32_t orig_pc_value = 0;
14301 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc, 0, &success);
14323 ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_pc, 0, &success);
14344 if (cond == 0xe || cond == 0xf || cond == UINT32_MAX)
14368 test_opcode = value_sp->GetValueAs<uint64_t>().value_or(0);
14373 if (test_opcode < 0x10000)
14464 row->GetCFAValue().SetIsRegisterPlusOffset(dwarf_sp, 0);