Lines Matching defs:opcode
891 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode,
921 if (ConditionPassed(opcode)) {
930 registers = Bits32(opcode, 7, 0);
932 if (Bit32(opcode, 8))
940 registers = Bits32(opcode, 15, 0) & ~0xa000;
946 Rt = Bits32(opcode, 15, 12);
953 registers = Bits32(opcode, 15, 0);
959 Rt = Bits32(opcode, 15, 12);
1014 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode,
1037 if (ConditionPassed(opcode)) {
1046 registers = Bits32(opcode, 7, 0);
1048 if (Bit32(opcode, 8))
1056 registers = Bits32(opcode, 15, 0) & ~0x2000;
1059 if (BitCount(registers) < 2 || (Bit32(opcode, 15) && Bit32(opcode, 14)))
1067 Rt = Bits32(opcode, 15, 12);
1077 registers = Bits32(opcode, 15, 0);
1083 if (BitIsSet(opcode, 13) && ArchVersion() >= ARMv7)
1087 Rt = Bits32(opcode, 15, 12);
1142 bool EmulateInstructionARM::EmulateADDRdSPImm(const uint32_t opcode,
1164 if (ConditionPassed(opcode)) {
1173 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
1176 Rd = Bits32(opcode, 15, 12);
1177 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
1203 bool EmulateInstructionARM::EmulateMOVRdSP(const uint32_t opcode,
1225 if (ConditionPassed(opcode)) {
1258 bool EmulateInstructionARM::EmulateMOVLowHigh(const uint32_t opcode,
1260 return EmulateMOVRdRm(opcode, encoding);
1265 bool EmulateInstructionARM::EmulateMOVRdRm(const uint32_t opcode,
1287 if (ConditionPassed(opcode)) {
1293 Rd = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
1294 Rm = Bits32(opcode, 6, 3);
1300 Rd = Bits32(opcode, 2, 0);
1301 Rm = Bits32(opcode, 5, 3);
1307 Rd = Bits32(opcode, 11, 8);
1308 Rm = Bits32(opcode, 3, 0);
1309 setflags = BitIsSet(opcode, 20);
1319 Rd = Bits32(opcode, 15, 12);
1320 Rm = Bits32(opcode, 3, 0);
1321 setflags = BitIsSet(opcode, 20);
1326 return EmulateSUBSPcLrEtc(opcode, encoding);
1356 bool EmulateInstructionARM::EmulateMOVRdImm(const uint32_t opcode,
1376 if (ConditionPassed(opcode)) {
1386 Rd = Bits32(opcode, 10, 8);
1388 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
1394 Rd = Bits32(opcode, 11, 8);
1395 setflags = BitIsSet(opcode, 20);
1396 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1405 Rd = Bits32(opcode, 11, 8);
1407 uint32_t imm4 = Bits32(opcode, 19, 16);
1408 uint32_t imm3 = Bits32(opcode, 14, 12);
1409 uint32_t i = Bit32(opcode, 26);
1410 uint32_t imm8 = Bits32(opcode, 7, 0);
1421 Rd = Bits32(opcode, 15, 12);
1422 setflags = BitIsSet(opcode, 20);
1423 imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1428 return EmulateSUBSPcLrEtc(opcode, encoding);
1434 Rd = Bits32(opcode, 15, 12);
1436 uint32_t imm4 = Bits32(opcode, 19, 16);
1437 uint32_t imm12 = Bits32(opcode, 11, 0);
1469 bool EmulateInstructionARM::EmulateMUL(const uint32_t opcode,
1487 if (ConditionPassed(opcode)) {
1497 d = Bits32(opcode, 2, 0);
1498 n = Bits32(opcode, 5, 3);
1499 m = Bits32(opcode, 2, 0);
1510 d = Bits32(opcode, 11, 8);
1511 n = Bits32(opcode, 19, 16);
1512 m = Bits32(opcode, 3, 0);
1523 d = Bits32(opcode, 19, 16);
1524 n = Bits32(opcode, 3, 0);
1525 m = Bits32(opcode, 11, 8);
1526 setflags = BitIsSet(opcode, 20);
1598 bool EmulateInstructionARM::EmulateMVNImm(const uint32_t opcode,
1618 if (ConditionPassed(opcode)) {
1625 Rd = Bits32(opcode, 11, 8);
1626 setflags = BitIsSet(opcode, 20);
1627 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry);
1630 Rd = Bits32(opcode, 15, 12);
1631 setflags = BitIsSet(opcode, 20);
1632 imm32 = ARMExpandImm_C(opcode, APSR_C, carry);
1637 return EmulateSUBSPcLrEtc(opcode, encoding);
1658 bool EmulateInstructionARM::EmulateMVNReg(const uint32_t opcode,
1679 if (ConditionPassed(opcode)) {
1688 Rd = Bits32(opcode, 2, 0);
1689 Rm = Bits32(opcode, 5, 3);
1697 Rd = Bits32(opcode, 11, 8);
1698 Rm = Bits32(opcode, 3, 0);
1699 setflags = BitIsSet(opcode, 20);
1700 shift_n = DecodeImmShiftThumb(opcode, shift_t);
1706 Rd = Bits32(opcode, 15, 12);
1707 Rm = Bits32(opcode, 3, 0);
1708 setflags = BitIsSet(opcode, 20);
1709 shift_n = DecodeImmShiftARM(opcode, shift_t);
1739 bool EmulateInstructionARM::EmulateLDRRtPCRelative(const uint32_t opcode,
1761 if (ConditionPassed(opcode)) {
1782 Rt = Bits32(opcode, 10, 8);
1783 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1787 Rt = Bits32(opcode, 15, 12);
1788 imm32 = Bits32(opcode, 11, 0) << 2; // imm32 = ZeroExtend(imm12, 32);
1789 add = BitIsSet(opcode, 23);
1827 bool EmulateInstructionARM::EmulateADDSPImm(const uint32_t opcode,
1849 if (ConditionPassed(opcode)) {
1859 d = Bits32(opcode, 10, 8);
1860 imm32 = (Bits32(opcode, 7, 0) << 2);
1867 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
1874 d = Bits32(opcode, 11, 8);
1875 imm32 = ThumbExpandImm(opcode);
1876 setflags = Bit32(opcode, 20);
1890 d = Bits32(opcode, 11, 8);
1892 uint32_t i = Bit32(opcode, 26);
1893 uint32_t imm3 = Bits32(opcode, 14, 12);
1894 uint32_t imm8 = Bits32(opcode, 7, 0);
1938 bool EmulateInstructionARM::EmulateADDSPRm(const uint32_t opcode,
1961 if (ConditionPassed(opcode)) {
1968 Rm = Bits32(opcode, 6, 3);
1998 bool EmulateInstructionARM::EmulateBLXImmediate(const uint32_t opcode,
2020 if (ConditionPassed(opcode)) {
2032 uint32_t S = Bit32(opcode, 26);
2033 uint32_t imm10 = Bits32(opcode, 25, 16);
2034 uint32_t J1 = Bit32(opcode, 13);
2035 uint32_t J2 = Bit32(opcode, 11);
2036 uint32_t imm11 = Bits32(opcode, 10, 0);
2051 uint32_t S = Bit32(opcode, 26);
2052 uint32_t imm10H = Bits32(opcode, 25, 16);
2053 uint32_t J1 = Bit32(opcode, 13);
2054 uint32_t J2 = Bit32(opcode, 11);
2055 uint32_t imm10L = Bits32(opcode, 10, 1);
2070 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2077 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2 |
2078 Bits32(opcode, 24, 24) << 1);
2102 bool EmulateInstructionARM::EmulateBLXRm(const uint32_t opcode,
2122 if (ConditionPassed(opcode)) {
2133 Rm = Bits32(opcode, 6, 3);
2142 Rm = Bits32(opcode, 3, 0);
2167 bool EmulateInstructionARM::EmulateBXRm(const uint32_t opcode,
2178 if (ConditionPassed(opcode)) {
2184 Rm = Bits32(opcode, 6, 3);
2189 Rm = Bits32(opcode, 3, 0);
2215 bool EmulateInstructionARM::EmulateBXJRm(const uint32_t opcode,
2232 if (ConditionPassed(opcode)) {
2238 Rm = Bits32(opcode, 19, 16);
2245 Rm = Bits32(opcode, 3, 0);
2268 bool EmulateInstructionARM::EmulateSUBR7IPImm(const uint32_t opcode,
2288 if (ConditionPassed(opcode)) {
2296 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2318 bool EmulateInstructionARM::EmulateSUBIPSPImm(const uint32_t opcode,
2338 if (ConditionPassed(opcode)) {
2346 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2371 bool EmulateInstructionARM::EmulateSUBSPImm(const uint32_t opcode,
2392 if (ConditionPassed(opcode)) {
2404 imm32 = ThumbImm7Scaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
2407 Rd = Bits32(opcode, 11, 8);
2408 setflags = BitIsSet(opcode, 20);
2409 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2411 return EmulateCMPImm(opcode, eEncodingT2);
2416 Rd = Bits32(opcode, 11, 8);
2418 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
2423 Rd = Bits32(opcode, 15, 12);
2424 setflags = BitIsSet(opcode, 20);
2425 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
2430 return EmulateSUBSPcLrEtc(opcode, encoding);
2457 bool EmulateInstructionARM::EmulateSTRRtSP(const uint32_t opcode,
2472 if (ConditionPassed(opcode)) {
2487 Rt = Bits32(opcode, 15, 12);
2488 imm12 = Bits32(opcode, 11, 0);
2489 Rn = Bits32(opcode, 19, 16);
2494 index = BitIsSet(opcode, 24);
2495 add = BitIsSet(opcode, 23);
2496 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
2551 bool EmulateInstructionARM::EmulateVPUSH(const uint32_t opcode,
2574 if (ConditionPassed(opcode)) {
2587 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2588 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2590 regs = Bits32(opcode, 7, 0) / 2;
2598 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2599 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2600 regs = Bits32(opcode, 7, 0);
2644 bool EmulateInstructionARM::EmulateVPOP(const uint32_t opcode,
2666 if (ConditionPassed(opcode)) {
2679 d = Bit32(opcode, 22) << 4 | Bits32(opcode, 15, 12);
2680 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2682 regs = Bits32(opcode, 7, 0) / 2;
2690 d = Bits32(opcode, 15, 12) << 1 | Bit32(opcode, 22);
2691 imm32 = Bits32(opcode, 7, 0) * addr_byte_size;
2692 regs = Bits32(opcode, 7, 0);
2733 bool EmulateInstructionARM::EmulateSVC(const uint32_t opcode,
2746 if (ConditionPassed(opcode)) {
2756 imm32 = Bits32(opcode, 7, 0);
2761 imm32 = Bits32(opcode, 23, 0);
2779 bool EmulateInstructionARM::EmulateIT(const uint32_t opcode,
2787 m_it_session.InitIT(Bits32(opcode, 7, 0));
2791 bool EmulateInstructionARM::EmulateNop(const uint32_t opcode,
2798 bool EmulateInstructionARM::EmulateB(const uint32_t opcode,
2811 if (ConditionPassed(opcode)) {
2822 imm32 = llvm::SignExtend32<9>(Bits32(opcode, 7, 0) << 1);
2827 imm32 = llvm::SignExtend32<12>(Bits32(opcode, 10, 0) << 1);
2834 if (Bits32(opcode, 25, 23) == 7)
2838 uint32_t S = Bit32(opcode, 26);
2839 uint32_t imm6 = Bits32(opcode, 21, 16);
2840 uint32_t J1 = Bit32(opcode, 13);
2841 uint32_t J2 = Bit32(opcode, 11);
2842 uint32_t imm11 = Bits32(opcode, 10, 0);
2851 uint32_t S = Bit32(opcode, 26);
2852 uint32_t imm10 = Bits32(opcode, 25, 16);
2853 uint32_t J1 = Bit32(opcode, 13);
2854 uint32_t J2 = Bit32(opcode, 11);
2855 uint32_t imm11 = Bits32(opcode, 10, 0);
2866 imm32 = llvm::SignExtend32<26>(Bits32(opcode, 23, 0) << 2);
2882 bool EmulateInstructionARM::EmulateCB(const uint32_t opcode,
2894 uint32_t reg_val = ReadCoreReg(Bits32(opcode, 2, 0), &success);
2909 imm32 = Bit32(opcode, 9) << 6 | Bits32(opcode, 7, 3) << 1;
2910 nonzero = BitIsSet(opcode, 11);
2936 bool EmulateInstructionARM::EmulateTB(const uint32_t opcode,
2950 if (ConditionPassed(opcode)) {
2958 Rn = Bits32(opcode, 19, 16);
2959 Rm = Bits32(opcode, 3, 0);
2960 is_tbh = BitIsSet(opcode, 4);
3010 bool EmulateInstructionARM::EmulateADDImmThumb(const uint32_t opcode,
3026 if (ConditionPassed(opcode)) {
3038 d = Bits32(opcode, 2, 0);
3039 n = Bits32(opcode, 5, 3);
3041 imm32 = Bits32(opcode, 8, 6);
3048 d = Bits32(opcode, 10, 8);
3049 n = Bits32(opcode, 10, 8);
3051 imm32 = Bits32(opcode, 7, 0);
3059 d = Bits32(opcode, 11, 8);
3060 n = Bits32(opcode, 19, 16);
3061 setflags = BitIsSet(opcode, 20);
3062 imm32 = ThumbExpandImm_C(opcode, APSR_C, carry_out);
3066 return EmulateADDSPImm(opcode, eEncodingT3);
3078 d = Bits32(opcode, 11, 8);
3079 n = Bits32(opcode, 19, 16);
3081 uint32_t i = Bit32(opcode, 26);
3082 uint32_t imm3 = Bits32(opcode, 14, 12);
3083 uint32_t imm8 = Bits32(opcode, 7, 0);
3088 return EmulateADDSPImm(opcode, eEncodingT4);
3131 bool EmulateInstructionARM::EmulateADDImmARM(const uint32_t opcode,
3151 if (ConditionPassed(opcode)) {
3158 Rd = Bits32(opcode, 15, 12);
3159 Rn = Bits32(opcode, 19, 16);
3160 setflags = BitIsSet(opcode, 20);
3161 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3196 bool EmulateInstructionARM::EmulateADDReg(const uint32_t opcode,
3217 if (ConditionPassed(opcode)) {
3224 Rd = Bits32(opcode, 2, 0);
3225 Rn = Bits32(opcode, 5, 3);
3226 Rm = Bits32(opcode, 8, 6);
3232 Rd = Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3233 Rm = Bits32(opcode, 6, 3);
3243 Rd = Bits32(opcode, 15, 12);
3244 Rn = Bits32(opcode, 19, 16);
3245 Rm = Bits32(opcode, 3, 0);
3246 setflags = BitIsSet(opcode, 20);
3247 shift_n = DecodeImmShiftARM(opcode, shift_t);
3285 bool EmulateInstructionARM::EmulateCMNImm(const uint32_t opcode,
3304 Rn = Bits32(opcode, 19, 16);
3305 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
3310 Rn = Bits32(opcode, 19, 16);
3311 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3332 bool EmulateInstructionARM::EmulateCMNReg(const uint32_t opcode,
3354 Rn = Bits32(opcode, 2, 0);
3355 Rm = Bits32(opcode, 5, 3);
3360 Rn = Bits32(opcode, 19, 16);
3361 Rm = Bits32(opcode, 3, 0);
3362 shift_n = DecodeImmShiftThumb(opcode, shift_t);
3368 Rn = Bits32(opcode, 19, 16);
3369 Rm = Bits32(opcode, 3, 0);
3370 shift_n = DecodeImmShiftARM(opcode, shift_t);
3398 bool EmulateInstructionARM::EmulateCMPImm(const uint32_t opcode,
3417 Rn = Bits32(opcode, 10, 8);
3418 imm32 = Bits32(opcode, 7, 0);
3421 Rn = Bits32(opcode, 19, 16);
3422 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
3427 Rn = Bits32(opcode, 19, 16);
3428 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
3449 bool EmulateInstructionARM::EmulateCMPReg(const uint32_t opcode,
3471 Rn = Bits32(opcode, 2, 0);
3472 Rm = Bits32(opcode, 5, 3);
3477 Rn = Bit32(opcode, 7) << 3 | Bits32(opcode, 2, 0);
3478 Rm = Bits32(opcode, 6, 3);
3487 Rn = Bits32(opcode, 19, 16);
3488 Rm = Bits32(opcode, 3, 0);
3489 shift_n = DecodeImmShiftThumb(opcode, shift_t);
3494 Rn = Bits32(opcode, 19, 16);
3495 Rm = Bits32(opcode, 3, 0);
3496 shift_n = DecodeImmShiftARM(opcode, shift_t);
3526 bool EmulateInstructionARM::EmulateASRImm(const uint32_t opcode,
3544 return EmulateShiftImm(opcode, encoding, SRType_ASR);
3552 bool EmulateInstructionARM::EmulateASRReg(const uint32_t opcode,
3568 return EmulateShiftReg(opcode, encoding, SRType_ASR);
3574 bool EmulateInstructionARM::EmulateLSLImm(const uint32_t opcode,
3592 return EmulateShiftImm(opcode, encoding, SRType_LSL);
3599 bool EmulateInstructionARM::EmulateLSLReg(const uint32_t opcode,
3615 return EmulateShiftReg(opcode, encoding, SRType_LSL);
3622 bool EmulateInstructionARM::EmulateLSRImm(const uint32_t opcode,
3640 return EmulateShiftImm(opcode, encoding, SRType_LSR);
3647 bool EmulateInstructionARM::EmulateLSRReg(const uint32_t opcode,
3663 return EmulateShiftReg(opcode, encoding, SRType_LSR);
3670 bool EmulateInstructionARM::EmulateRORImm(const uint32_t opcode,
3688 return EmulateShiftImm(opcode, encoding, SRType_ROR);
3696 bool EmulateInstructionARM::EmulateRORReg(const uint32_t opcode,
3712 return EmulateShiftReg(opcode, encoding, SRType_ROR);
3720 bool EmulateInstructionARM::EmulateRRX(const uint32_t opcode,
3738 return EmulateShiftImm(opcode, encoding, SRType_RRX);
3741 bool EmulateInstructionARM::EmulateShiftImm(const uint32_t opcode,
3752 if (ConditionPassed(opcode)) {
3771 Rd = Bits32(opcode, 2, 0);
3772 Rm = Bits32(opcode, 5, 3);
3774 imm5 = Bits32(opcode, 10, 6);
3782 Rd = Bits32(opcode, 11, 8);
3783 Rm = Bits32(opcode, 3, 0);
3784 setflags = BitIsSet(opcode, 20);
3785 imm5 = Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6);
3790 Rd = Bits32(opcode, 15, 12);
3791 Rm = Bits32(opcode, 3, 0);
3792 setflags = BitIsSet(opcode, 20);
3793 imm5 = Bits32(opcode, 11, 7);
3827 bool EmulateInstructionARM::EmulateShiftReg(const uint32_t opcode,
3837 if (ConditionPassed(opcode)) {
3846 Rd = Bits32(opcode, 2, 0);
3848 Rm = Bits32(opcode, 5, 3);
3852 Rd = Bits32(opcode, 11, 8);
3853 Rn = Bits32(opcode, 19, 16);
3854 Rm = Bits32(opcode, 3, 0);
3855 setflags = BitIsSet(opcode, 20);
3860 Rd = Bits32(opcode, 15, 12);
3861 Rn = Bits32(opcode, 3, 0);
3862 Rm = Bits32(opcode, 11, 8);
3863 setflags = BitIsSet(opcode, 20);
3901 bool EmulateInstructionARM::EmulateLDM(const uint32_t opcode,
3921 if (ConditionPassed(opcode)) {
3930 n = Bits32(opcode, 10, 8);
3931 registers = Bits32(opcode, 7, 0);
3941 n = Bits32(opcode, 19, 16);
3942 registers = Bits32(opcode, 15, 0);
3944 wback = BitIsSet(opcode, 21);
3949 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15)))
3963 n = Bits32(opcode, 19, 16);
3964 registers = Bits32(opcode, 15, 0);
3965 wback = BitIsSet(opcode, 21);
4044 bool EmulateInstructionARM::EmulateLDMDA(const uint32_t opcode,
4065 if (ConditionPassed(opcode)) {
4075 n = Bits32(opcode, 19, 16);
4076 registers = Bits32(opcode, 15, 0);
4077 wback = BitIsSet(opcode, 21);
4159 bool EmulateInstructionARM::EmulateLDMDB(const uint32_t opcode,
4179 if (ConditionPassed(opcode)) {
4187 n = Bits32(opcode, 19, 16);
4188 registers = Bits32(opcode, 15, 0);
4190 wback = BitIsSet(opcode, 21);
4195 (BitIsSet(opcode, 14) && BitIsSet(opcode, 15)))
4211 n = Bits32(opcode, 19, 16);
4212 registers = Bits32(opcode, 15, 0);
4213 wback = BitIsSet(opcode, 21);
4296 bool EmulateInstructionARM::EmulateLDMIB(const uint32_t opcode,
4315 if (ConditionPassed(opcode)) {
4323 n = Bits32(opcode, 19, 16);
4324 registers = Bits32(opcode, 15, 0);
4325 wback = BitIsSet(opcode, 21);
4406 bool EmulateInstructionARM::EmulateLDRRtRnImm(const uint32_t opcode,
4427 if (ConditionPassed(opcode)) {
4437 Rt = Bits32(opcode, 2, 0);
4438 Rn = Bits32(opcode, 5, 3);
4439 imm32 = Bits32(opcode, 10, 6) << 2; // imm32 = ZeroExtend(imm5:'00', 32);
4449 Rt = Bits32(opcode, 10, 8);
4451 imm32 = Bits32(opcode, 7, 0) << 2;
4463 Rt = Bits32(opcode, 15, 12);
4464 Rn = Bits32(opcode, 19, 16);
4465 imm32 = Bits32(opcode, 11, 0);
4484 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))
4488 Rt = Bits32(opcode, 15, 12);
4489 Rn = Bits32(opcode, 19, 16);
4490 imm32 = Bits32(opcode, 7, 0);
4493 index = BitIsSet(opcode, 10);
4494 add = BitIsSet(opcode, 9);
4495 wback = BitIsSet(opcode, 8);
4569 bool EmulateInstructionARM::EmulateSTM(const uint32_t opcode,
4591 if (ConditionPassed(opcode)) {
4601 n = Bits32(opcode, 10, 8);
4602 registers = Bits32(opcode, 7, 0);
4614 n = Bits32(opcode, 19, 16);
4615 registers = Bits32(opcode, 15, 0);
4617 wback = BitIsSet(opcode, 21);
4631 n = Bits32(opcode, 19, 16);
4632 registers = Bits32(opcode, 15, 0);
4633 wback = BitIsSet(opcode, 21);
4721 bool EmulateInstructionARM::EmulateSTMDA(const uint32_t opcode,
4744 if (ConditionPassed(opcode)) {
4754 n = Bits32(opcode, 19, 16);
4755 registers = Bits32(opcode, 15, 0);
4756 wback = BitIsSet(opcode, 21);
4843 bool EmulateInstructionARM::EmulateSTMDB(const uint32_t opcode,
4866 if (ConditionPassed(opcode)) {
4876 if ((BitIsSet(opcode, 21)) && (Bits32(opcode, 19, 16) == 13)) {
4880 n = Bits32(opcode, 19, 16);
4881 registers = Bits32(opcode, 15, 0);
4883 wback = BitIsSet(opcode, 21);
4895 if (BitIsSet(opcode, 21) && (Bits32(opcode, 19, 16) == 13) &&
4896 BitCount(Bits32(opcode, 15, 0)) >= 2) {
4900 n = Bits32(opcode, 19, 16);
4901 registers = Bits32(opcode, 15, 0);
4902 wback = BitIsSet(opcode, 21);
4992 bool EmulateInstructionARM::EmulateSTMIB(const uint32_t opcode,
5015 if (ConditionPassed(opcode)) {
5025 n = Bits32(opcode, 19, 16);
5026 registers = Bits32(opcode, 15, 0);
5027 wback = BitIsSet(opcode, 21);
5114 bool EmulateInstructionARM::EmulateSTRThumb(const uint32_t opcode,
5130 if (ConditionPassed(opcode)) {
5143 t = Bits32(opcode, 2, 0);
5144 n = Bits32(opcode, 5, 3);
5145 imm32 = Bits32(opcode, 10, 6) << 2;
5155 t = Bits32(opcode, 10, 8);
5157 imm32 = Bits32(opcode, 7, 0) << 2;
5167 if (Bits32(opcode, 19, 16) == 15)
5171 t = Bits32(opcode, 15, 12);
5172 n = Bits32(opcode, 19, 16);
5173 imm32 = Bits32(opcode, 11, 0);
5190 if ((Bits32(opcode, 19, 16) == 15) ||
5191 (BitIsClear(opcode, 10) && BitIsClear(opcode, 8)))
5195 t = Bits32(opcode, 15, 12);
5196 n = Bits32(opcode, 19, 16);
5197 imm32 = Bits32(opcode, 7, 0);
5200 index = BitIsSet(opcode, 10);
5201 add = BitIsSet(opcode, 9);
5202 wback = BitIsSet(opcode, 8);
5281 bool EmulateInstructionARM::EmulateSTRRegister(const uint32_t opcode,
5302 if (ConditionPassed(opcode)) {
5320 t = Bits32(opcode, 2, 0);
5321 n = Bits32(opcode, 5, 3);
5322 m = Bits32(opcode, 8, 6);
5336 if (Bits32(opcode, 19, 16) == 15)
5340 t = Bits32(opcode, 15, 12);
5341 n = Bits32(opcode, 19, 16);
5342 m = Bits32(opcode, 3, 0);
5351 shift_n = Bits32(opcode, 5, 4);
5361 t = Bits32(opcode, 15, 12);
5362 n = Bits32(opcode, 19, 16);
5363 m = Bits32(opcode, 3, 0);
5367 index = BitIsSet(opcode, 24);
5368 add = BitIsSet(opcode, 23);
5369 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
5372 uint32_t typ = Bits32(opcode, 6, 5);
5373 uint32_t imm5 = Bits32(opcode, 11, 7);
5470 bool EmulateInstructionARM::EmulateSTRBThumb(const uint32_t opcode,
5483 if (ConditionPassed(opcode)) {
5494 t = Bits32(opcode, 2, 0);
5495 n = Bits32(opcode, 5, 3);
5496 imm32 = Bits32(opcode, 10, 6);
5506 if (Bits32(opcode, 19, 16) == 15)
5510 t = Bits32(opcode, 15, 12);
5511 n = Bits32(opcode, 19, 16);
5512 imm32 = Bits32(opcode, 11, 0);
5527 if (Bits32(opcode, 19, 16) == 15)
5531 t = Bits32(opcode, 15, 12);
5532 n = Bits32(opcode, 19, 16);
5533 imm32 = Bits32(opcode, 7, 0);
5536 index = BitIsSet(opcode, 10);
5537 add = BitIsSet(opcode, 9);
5538 wback = BitIsSet(opcode, 8);
5606 bool EmulateInstructionARM::EmulateSTRHRegister(const uint32_t opcode,
5623 if (ConditionPassed(opcode)) {
5639 t = Bits32(opcode, 2, 0);
5640 n = Bits32(opcode, 5, 3);
5641 m = Bits32(opcode, 8, 6);
5657 t = Bits32(opcode, 15, 12);
5658 n = Bits32(opcode, 19, 16);
5659 m = Bits32(opcode, 3, 0);
5670 shift_n = Bits32(opcode, 5, 4);
5681 t = Bits32(opcode, 15, 12);
5682 n = Bits32(opcode, 19, 16);
5683 m = Bits32(opcode, 3, 0);
5687 index = BitIsSet(opcode, 24);
5688 add = BitIsSet(opcode, 23);
5689 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
5780 bool EmulateInstructionARM::EmulateADCImm(const uint32_t opcode,
5800 if (ConditionPassed(opcode)) {
5807 Rd = Bits32(opcode, 11, 8);
5808 Rn = Bits32(opcode, 19, 16);
5809 setflags = BitIsSet(opcode, 20);
5810 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
5815 Rd = Bits32(opcode, 15, 12);
5816 Rn = Bits32(opcode, 19, 16);
5817 setflags = BitIsSet(opcode, 20);
5818 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5821 return EmulateSUBSPcLrEtc(opcode, encoding);
5849 bool EmulateInstructionARM::EmulateADCReg(const uint32_t opcode,
5870 if (ConditionPassed(opcode)) {
5877 Rd = Rn = Bits32(opcode, 2, 0);
5878 Rm = Bits32(opcode, 5, 3);
5884 Rd = Bits32(opcode, 11, 8);
5885 Rn = Bits32(opcode, 19, 16);
5886 Rm = Bits32(opcode, 3, 0);
5887 setflags = BitIsSet(opcode, 20);
5888 shift_n = DecodeImmShiftThumb(opcode, shift_t);
5893 Rd = Bits32(opcode, 15, 12);
5894 Rn = Bits32(opcode, 19, 16);
5895 Rm = Bits32(opcode, 3, 0);
5896 setflags = BitIsSet(opcode, 20);
5897 shift_n = DecodeImmShiftARM(opcode, shift_t);
5900 return EmulateSUBSPcLrEtc(opcode, encoding);
5934 bool EmulateInstructionARM::EmulateADR(const uint32_t opcode,
5949 if (ConditionPassed(opcode)) {
5955 Rd = Bits32(opcode, 10, 8);
5956 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32)
5961 Rd = Bits32(opcode, 11, 8);
5962 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
5963 add = (Bits32(opcode, 24, 21) == 0); // 0b0000 => ADD; 0b0101 => SUB
5969 Rd = Bits32(opcode, 15, 12);
5970 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
5971 add = (Bits32(opcode, 24, 21) == 0x4); // 0b0100 => ADD; 0b0010 => SUB
5997 bool EmulateInstructionARM::EmulateANDImm(const uint32_t opcode,
6017 if (ConditionPassed(opcode)) {
6025 Rd = Bits32(opcode, 11, 8);
6026 Rn = Bits32(opcode, 19, 16);
6027 setflags = BitIsSet(opcode, 20);
6029 opcode, APSR_C,
6033 return EmulateTSTImm(opcode, eEncodingT1);
6038 Rd = Bits32(opcode, 15, 12);
6039 Rn = Bits32(opcode, 19, 16);
6040 setflags = BitIsSet(opcode, 20);
6042 ARMExpandImm_C(opcode, APSR_C,
6046 return EmulateSUBSPcLrEtc(opcode, encoding);
6072 bool EmulateInstructionARM::EmulateANDReg(const uint32_t opcode,
6093 if (ConditionPassed(opcode)) {
6101 Rd = Rn = Bits32(opcode, 2, 0);
6102 Rm = Bits32(opcode, 5, 3);
6108 Rd = Bits32(opcode, 11, 8);
6109 Rn = Bits32(opcode, 19, 16);
6110 Rm = Bits32(opcode, 3, 0);
6111 setflags = BitIsSet(opcode, 20);
6112 shift_n = DecodeImmShiftThumb(opcode, shift_t);
6115 return EmulateTSTReg(opcode, eEncodingT2);
6120 Rd = Bits32(opcode, 15, 12);
6121 Rn = Bits32(opcode, 19, 16);
6122 Rm = Bits32(opcode, 3, 0);
6123 setflags = BitIsSet(opcode, 20);
6124 shift_n = DecodeImmShiftARM(opcode, shift_t);
6127 return EmulateSUBSPcLrEtc(opcode, encoding);
6162 bool EmulateInstructionARM::EmulateBICImm(const uint32_t opcode,
6182 if (ConditionPassed(opcode)) {
6190 Rd = Bits32(opcode, 11, 8);
6191 Rn = Bits32(opcode, 19, 16);
6192 setflags = BitIsSet(opcode, 20);
6194 opcode, APSR_C,
6200 Rd = Bits32(opcode, 15, 12);
6201 Rn = Bits32(opcode, 19, 16);
6202 setflags = BitIsSet(opcode, 20);
6204 ARMExpandImm_C(opcode, APSR_C,
6210 return EmulateSUBSPcLrEtc(opcode, encoding);
6237 bool EmulateInstructionARM::EmulateBICReg(const uint32_t opcode,
6258 if (ConditionPassed(opcode)) {
6266 Rd = Rn = Bits32(opcode, 2, 0);
6267 Rm = Bits32(opcode, 5, 3);
6273 Rd = Bits32(opcode, 11, 8);
6274 Rn = Bits32(opcode, 19, 16);
6275 Rm = Bits32(opcode, 3, 0);
6276 setflags = BitIsSet(opcode, 20);
6277 shift_n = DecodeImmShiftThumb(opcode, shift_t);
6282 Rd = Bits32(opcode, 15, 12);
6283 Rn = Bits32(opcode, 19, 16);
6284 Rm = Bits32(opcode, 3, 0);
6285 setflags = BitIsSet(opcode, 20);
6286 shift_n = DecodeImmShiftARM(opcode, shift_t);
6291 return EmulateSUBSPcLrEtc(opcode, encoding);
6326 bool EmulateInstructionARM::EmulateLDRImmediateARM(const uint32_t opcode,
6345 if (ConditionPassed(opcode)) {
6362 t = Bits32(opcode, 15, 12);
6363 n = Bits32(opcode, 19, 16);
6364 imm32 = Bits32(opcode, 11, 0);
6368 index = BitIsSet(opcode, 24);
6369 add = BitIsSet(opcode, 23);
6370 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
6462 bool EmulateInstructionARM::EmulateLDRRegister(const uint32_t opcode,
6485 if (ConditionPassed(opcode)) {
6502 t = Bits32(opcode, 2, 0);
6503 n = Bits32(opcode, 5, 3);
6504 m = Bits32(opcode, 8, 6);
6520 t = Bits32(opcode, 15, 12);
6521 n = Bits32(opcode, 19, 16);
6522 m = Bits32(opcode, 3, 0);
6531 shift_n = Bits32(opcode, 5, 4);
6546 t = Bits32(opcode, 15, 12);
6547 n = Bits32(opcode, 19, 16);
6548 m = Bits32(opcode, 3, 0);
6552 index = BitIsSet(opcode, 24);
6553 add = BitIsSet(opcode, 23);
6554 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
6557 uint32_t type = Bits32(opcode, 6, 5);
6558 uint32_t imm5 = Bits32(opcode, 11, 7);
6668 bool EmulateInstructionARM::EmulateLDRBImmediate(const uint32_t opcode,
6681 if (ConditionPassed(opcode)) {
6693 t = Bits32(opcode, 2, 0);
6694 n = Bits32(opcode, 5, 3);
6695 imm32 = Bits32(opcode, 10, 6);
6706 t = Bits32(opcode, 15, 12);
6707 n = Bits32(opcode, 19, 16);
6708 imm32 = Bits32(opcode, 11, 0);
6721 return EmulateLDRBLiteral(opcode, eEncodingT1);
6732 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))
6736 t = Bits32(opcode, 15, 12);
6737 n = Bits32(opcode, 19, 16);
6738 imm32 = Bits32(opcode, 7, 0);
6741 index = BitIsSet(opcode, 10);
6742 add = BitIsSet(opcode, 9);
6743 wback = BitIsSet(opcode, 8);
6751 return EmulateLDRBLiteral(opcode, eEncodingT1);
6815 bool EmulateInstructionARM::EmulateLDRBLiteral(const uint32_t opcode,
6827 if (ConditionPassed(opcode)) {
6834 t = Bits32(opcode, 15, 12);
6835 imm32 = Bits32(opcode, 11, 0);
6836 add = BitIsSet(opcode, 23);
6850 t = Bits32(opcode, 15, 12);
6851 imm32 = Bits32(opcode, 11, 0);
6852 add = BitIsSet(opcode, 23);
6896 bool EmulateInstructionARM::EmulateLDRBRegister(const uint32_t opcode,
6910 if (ConditionPassed(opcode)) {
6924 t = Bits32(opcode, 2, 0);
6925 n = Bits32(opcode, 5, 3);
6926 m = Bits32(opcode, 8, 6);
6940 t = Bits32(opcode, 15, 12);
6941 n = Bits32(opcode, 19, 16);
6942 m = Bits32(opcode, 3, 0);
6951 shift_n = Bits32(opcode, 5, 4);
6959 return EmulateLDRBLiteral(opcode, eEncodingT1);
6969 t = Bits32(opcode, 15, 12);
6970 n = Bits32(opcode, 19, 16);
6971 m = Bits32(opcode, 3, 0);
6975 index = BitIsSet(opcode, 24);
6976 add = BitIsSet(opcode, 23);
6977 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
6980 uint32_t type = Bits32(opcode, 6, 5);
6981 uint32_t imm5 = Bits32(opcode, 11, 7);
7058 bool EmulateInstructionARM::EmulateLDRHImmediate(const uint32_t opcode,
7075 if (ConditionPassed(opcode)) {
7087 t = Bits32(opcode, 2, 0);
7088 n = Bits32(opcode, 5, 3);
7089 imm32 = Bits32(opcode, 10, 6) << 1;
7102 t = Bits32(opcode, 15, 12);
7103 n = Bits32(opcode, 19, 16);
7104 imm32 = Bits32(opcode, 11, 0);
7122 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))
7126 t = Bits32(opcode, 15, 12);
7127 n = Bits32(opcode, 19, 16);
7128 imm32 = Bits32(opcode, 7, 0);
7131 index = BitIsSet(opcode, 10);
7132 add = BitIsSet(opcode, 9);
7133 wback = BitIsSet(opcode, 8);
7205 bool EmulateInstructionARM::EmulateLDRHLiteral(const uint32_t opcode,
7221 if (ConditionPassed(opcode)) {
7231 t = Bits32(opcode, 15, 12);
7232 imm32 = Bits32(opcode, 11, 0);
7233 add = BitIsSet(opcode, 23);
7242 uint32_t imm4H = Bits32(opcode, 11, 8);
7243 uint32_t imm4L = Bits32(opcode, 3, 0);
7246 t = Bits32(opcode, 15, 12);
7248 add = BitIsSet(opcode, 23);
7309 bool EmulateInstructionARM::EmulateLDRHRegister(const uint32_t opcode,
7327 if (ConditionPassed(opcode)) {
7343 t = Bits32(opcode, 2, 0);
7344 n = Bits32(opcode, 5, 3);
7345 m = Bits32(opcode, 8, 6);
7362 t = Bits32(opcode, 15, 12);
7363 n = Bits32(opcode, 19, 16);
7364 m = Bits32(opcode, 3, 0);
7373 shift_n = Bits32(opcode, 5, 4);
7383 t = Bits32(opcode, 15, 12);
7384 n = Bits32(opcode, 19, 16);
7385 m = Bits32(opcode, 3, 0);
7389 index = BitIsSet(opcode, 24);
7390 add = BitIsSet(opcode, 23);
7391 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
7485 bool EmulateInstructionARM::EmulateLDRSBImmediate(const uint32_t opcode,
7498 if (ConditionPassed(opcode)) {
7512 t = Bits32(opcode, 15, 12);
7513 n = Bits32(opcode, 19, 16);
7514 imm32 = Bits32(opcode, 11, 0);
7532 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))
7536 t = Bits32(opcode, 15, 12);
7537 n = Bits32(opcode, 19, 16);
7538 imm32 = Bits32(opcode, 7, 0);
7541 index = BitIsSet(opcode, 10);
7542 add = BitIsSet(opcode, 9);
7543 wback = BitIsSet(opcode, 8);
7547 ((t == 15) && (BitIsClear(opcode, 10) || BitIsSet(opcode, 9) ||
7548 BitIsSet(opcode, 8)))) ||
7558 t = Bits32(opcode, 15, 12);
7559 n = Bits32(opcode, 19, 16);
7561 uint32_t imm4H = Bits32(opcode, 11, 8);
7562 uint32_t imm4L = Bits32(opcode, 3, 0);
7567 index = BitIsSet(opcode, 24);
7568 add = BitIsSet(opcode, 23);
7569 wback = (BitIsClear(opcode, 24) || BitIsSet(opcode, 21));
7634 bool EmulateInstructionARM::EmulateLDRSBLiteral(const uint32_t opcode,
7646 if (ConditionPassed(opcode)) {
7656 t = Bits32(opcode, 15, 12);
7657 imm32 = Bits32(opcode, 11, 0);
7658 add = BitIsSet(opcode, 23);
7668 t = Bits32(opcode, 15, 12);
7669 uint32_t imm4H = Bits32(opcode, 11, 8);
7670 uint32_t imm4L = Bits32(opcode, 3, 0);
7672 add = BitIsSet(opcode, 23);
7722 bool EmulateInstructionARM::EmulateLDRSBRegister(const uint32_t opcode,
7736 if (ConditionPassed(opcode)) {
7750 t = Bits32(opcode, 2, 0);
7751 n = Bits32(opcode, 5, 3);
7752 m = Bits32(opcode, 8, 6);
7769 t = Bits32(opcode, 15, 12);
7770 n = Bits32(opcode, 19, 16);
7771 m = Bits32(opcode, 3, 0);
7780 shift_n = Bits32(opcode, 5, 4);
7790 t = Bits32(opcode, 15, 12);
7791 n = Bits32(opcode, 19, 16);
7792 m = Bits32(opcode, 3, 0);
7796 index = BitIsSet(opcode, 24);
7797 add = BitIsSet(opcode, 23);
7798 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
7882 bool EmulateInstructionARM::EmulateLDRSHImmediate(const uint32_t opcode,
7899 if (ConditionPassed(opcode)) {
7913 t = Bits32(opcode, 15, 12);
7914 n = Bits32(opcode, 19, 16);
7915 imm32 = Bits32(opcode, 11, 0);
7934 if (BitIsClear(opcode, 10) && BitIsClear(opcode, 8))
7938 t = Bits32(opcode, 15, 12);
7939 n = Bits32(opcode, 19, 16);
7940 imm32 = Bits32(opcode, 7, 0);
7943 index = BitIsSet(opcode, 10);
7944 add = BitIsSet(opcode, 9);
7945 wback = BitIsSet(opcode, 8);
7957 t = Bits32(opcode, 15, 12);
7958 n = Bits32(opcode, 19, 16);
7959 uint32_t imm4H = Bits32(opcode, 11, 8);
7960 uint32_t imm4L = Bits32(opcode, 3, 0);
7965 index = BitIsSet(opcode, 24);
7966 add = BitIsSet(opcode, 23);
7967 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
8041 bool EmulateInstructionARM::EmulateLDRSHLiteral(const uint32_t opcode,
8057 if (ConditionPassed(opcode)) {
8067 t = Bits32(opcode, 15, 12);
8068 imm32 = Bits32(opcode, 11, 0);
8069 add = BitIsSet(opcode, 23);
8079 t = Bits32(opcode, 15, 12);
8080 uint32_t imm4H = Bits32(opcode, 11, 8);
8081 uint32_t imm4L = Bits32(opcode, 3, 0);
8083 add = BitIsSet(opcode, 23);
8142 bool EmulateInstructionARM::EmulateLDRSHRegister(const uint32_t opcode,
8160 if (ConditionPassed(opcode)) {
8176 t = Bits32(opcode, 2, 0);
8177 n = Bits32(opcode, 5, 3);
8178 m = Bits32(opcode, 8, 6);
8195 t = Bits32(opcode, 15, 12);
8196 n = Bits32(opcode, 19, 16);
8197 m = Bits32(opcode, 3, 0);
8206 shift_n = Bits32(opcode, 5, 4);
8217 t = Bits32(opcode, 15, 12);
8218 n = Bits32(opcode, 19, 16);
8219 m = Bits32(opcode, 3, 0);
8223 index = BitIsSet(opcode, 24);
8224 add = BitIsSet(opcode, 23);
8225 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
8321 bool EmulateInstructionARM::EmulateSXTB(const uint32_t opcode,
8332 if (ConditionPassed(opcode)) {
8341 d = Bits32(opcode, 2, 0);
8342 m = Bits32(opcode, 5, 3);
8349 d = Bits32(opcode, 11, 8);
8350 m = Bits32(opcode, 3, 0);
8351 rotation = Bits32(opcode, 5, 4) << 3;
8361 d = Bits32(opcode, 15, 12);
8362 m = Bits32(opcode, 3, 0);
8363 rotation = Bits32(opcode, 11, 10) << 3;
8406 bool EmulateInstructionARM::EmulateSXTH(const uint32_t opcode,
8417 if (ConditionPassed(opcode)) {
8426 d = Bits32(opcode, 2, 0);
8427 m = Bits32(opcode, 5, 3);
8434 d = Bits32(opcode, 11, 8);
8435 m = Bits32(opcode, 3, 0);
8436 rotation = Bits32(opcode, 5, 4) << 3;
8446 d = Bits32(opcode, 15, 12);
8447 m = Bits32(opcode, 3, 0);
8448 rotation = Bits32(opcode, 11, 10) << 3;
8491 bool EmulateInstructionARM::EmulateUXTB(const uint32_t opcode,
8502 if (ConditionPassed(opcode)) {
8511 d = Bits32(opcode, 2, 0);
8512 m = Bits32(opcode, 5, 3);
8519 d = Bits32(opcode, 11, 8);
8520 m = Bits32(opcode, 3, 0);
8521 rotation = Bits32(opcode, 5, 4) << 3;
8531 d = Bits32(opcode, 15, 12);
8532 m = Bits32(opcode, 3, 0);
8533 rotation = Bits32(opcode, 11, 10) << 3;
8574 bool EmulateInstructionARM::EmulateUXTH(const uint32_t opcode,
8585 if (ConditionPassed(opcode)) {
8593 d = Bits32(opcode, 2, 0);
8594 m = Bits32(opcode, 5, 3);
8601 d = Bits32(opcode, 11, 8);
8602 m = Bits32(opcode, 3, 0);
8603 rotation = Bits32(opcode, 5, 4) << 3;
8613 d = Bits32(opcode, 15, 12);
8614 m = Bits32(opcode, 3, 0);
8615 rotation = Bits32(opcode, 11, 10) << 3;
8655 bool EmulateInstructionARM::EmulateRFE(const uint32_t opcode,
8672 if (ConditionPassed(opcode)) {
8683 n = Bits32(opcode, 19, 16);
8684 wback = BitIsSet(opcode, 21);
8700 n = Bits32(opcode, 19, 16);
8701 wback = BitIsSet(opcode, 21);
8717 n = Bits32(opcode, 19, 16);
8720 wback = BitIsSet(opcode, 21);
8721 increment = BitIsSet(opcode, 23);
8722 wordhigher = (Bit32(opcode, 24) == Bit32(opcode, 23));
8801 bool EmulateInstructionARM::EmulateEORImm(const uint32_t opcode,
8821 if (ConditionPassed(opcode)) {
8829 Rd = Bits32(opcode, 11, 8);
8830 Rn = Bits32(opcode, 19, 16);
8831 setflags = BitIsSet(opcode, 20);
8833 opcode, APSR_C,
8837 return EmulateTEQImm(opcode, eEncodingT1);
8842 Rd = Bits32(opcode, 15, 12);
8843 Rn = Bits32(opcode, 19, 16);
8844 setflags = BitIsSet(opcode, 20);
8846 ARMExpandImm_C(opcode, APSR_C,
8852 return EmulateSUBSPcLrEtc(opcode, encoding);
8879 bool EmulateInstructionARM::EmulateEORReg(const uint32_t opcode,
8900 if (ConditionPassed(opcode)) {
8908 Rd = Rn = Bits32(opcode, 2, 0);
8909 Rm = Bits32(opcode, 5, 3);
8915 Rd = Bits32(opcode, 11, 8);
8916 Rn = Bits32(opcode, 19, 16);
8917 Rm = Bits32(opcode, 3, 0);
8918 setflags = BitIsSet(opcode, 20);
8919 shift_n = DecodeImmShiftThumb(opcode, shift_t);
8922 return EmulateTEQReg(opcode, eEncodingT1);
8927 Rd = Bits32(opcode, 15, 12);
8928 Rn = Bits32(opcode, 19, 16);
8929 Rm = Bits32(opcode, 3, 0);
8930 setflags = BitIsSet(opcode, 20);
8931 shift_n = DecodeImmShiftARM(opcode, shift_t);
8936 return EmulateSUBSPcLrEtc(opcode, encoding);
8970 bool EmulateInstructionARM::EmulateORRImm(const uint32_t opcode,
8990 if (ConditionPassed(opcode)) {
8998 Rd = Bits32(opcode, 11, 8);
8999 Rn = Bits32(opcode, 19, 16);
9000 setflags = BitIsSet(opcode, 20);
9002 opcode, APSR_C,
9006 return EmulateMOVRdImm(opcode, eEncodingT2);
9011 Rd = Bits32(opcode, 15, 12);
9012 Rn = Bits32(opcode, 19, 16);
9013 setflags = BitIsSet(opcode, 20);
9015 ARMExpandImm_C(opcode, APSR_C,
9019 return EmulateSUBSPcLrEtc(opcode, encoding);
9046 bool EmulateInstructionARM::EmulateORRReg(const uint32_t opcode,
9067 if (ConditionPassed(opcode)) {
9075 Rd = Rn = Bits32(opcode, 2, 0);
9076 Rm = Bits32(opcode, 5, 3);
9082 Rd = Bits32(opcode, 11, 8);
9083 Rn = Bits32(opcode, 19, 16);
9084 Rm = Bits32(opcode, 3, 0);
9085 setflags = BitIsSet(opcode, 20);
9086 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9089 return EmulateMOVRdRm(opcode, eEncodingT3);
9094 Rd = Bits32(opcode, 15, 12);
9095 Rn = Bits32(opcode, 19, 16);
9096 Rm = Bits32(opcode, 3, 0);
9097 setflags = BitIsSet(opcode, 20);
9098 shift_n = DecodeImmShiftARM(opcode, shift_t);
9101 return EmulateSUBSPcLrEtc(opcode, encoding);
9135 bool EmulateInstructionARM::EmulateRSBImm(const uint32_t opcode,
9162 Rd = Bits32(opcode, 2, 0);
9163 Rn = Bits32(opcode, 5, 3);
9168 Rd = Bits32(opcode, 11, 8);
9169 Rn = Bits32(opcode, 19, 16);
9170 setflags = BitIsSet(opcode, 20);
9171 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9176 Rd = Bits32(opcode, 15, 12);
9177 Rn = Bits32(opcode, 19, 16);
9178 setflags = BitIsSet(opcode, 20);
9179 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9184 return EmulateSUBSPcLrEtc(opcode, encoding);
9207 bool EmulateInstructionARM::EmulateRSBReg(const uint32_t opcode,
9236 Rd = Bits32(opcode, 11, 8);
9237 Rn = Bits32(opcode, 19, 16);
9238 Rm = Bits32(opcode, 3, 0);
9239 setflags = BitIsSet(opcode, 20);
9240 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9246 Rd = Bits32(opcode, 15, 12);
9247 Rn = Bits32(opcode, 19, 16);
9248 Rm = Bits32(opcode, 3, 0);
9249 setflags = BitIsSet(opcode, 20);
9250 shift_n = DecodeImmShiftARM(opcode, shift_t);
9255 return EmulateSUBSPcLrEtc(opcode, encoding);
9286 bool EmulateInstructionARM::EmulateRSCImm(const uint32_t opcode,
9313 Rd = Bits32(opcode, 15, 12);
9314 Rn = Bits32(opcode, 19, 16);
9315 setflags = BitIsSet(opcode, 20);
9316 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9321 return EmulateSUBSPcLrEtc(opcode, encoding);
9345 bool EmulateInstructionARM::EmulateRSCReg(const uint32_t opcode,
9374 Rd = Bits32(opcode, 15, 12);
9375 Rn = Bits32(opcode, 19, 16);
9376 Rm = Bits32(opcode, 3, 0);
9377 setflags = BitIsSet(opcode, 20);
9378 shift_n = DecodeImmShiftARM(opcode, shift_t);
9383 return EmulateSUBSPcLrEtc(opcode, encoding);
9415 bool EmulateInstructionARM::EmulateSBCImm(const uint32_t opcode,
9442 Rd = Bits32(opcode, 11, 8);
9443 Rn = Bits32(opcode, 19, 16);
9444 setflags = BitIsSet(opcode, 20);
9445 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9450 Rd = Bits32(opcode, 15, 12);
9451 Rn = Bits32(opcode, 19, 16);
9452 setflags = BitIsSet(opcode, 20);
9453 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9458 return EmulateSUBSPcLrEtc(opcode, encoding);
9483 bool EmulateInstructionARM::EmulateSBCReg(const uint32_t opcode,
9512 Rd = Rn = Bits32(opcode, 2, 0);
9513 Rm = Bits32(opcode, 5, 3);
9519 Rd = Bits32(opcode, 11, 8);
9520 Rn = Bits32(opcode, 19, 16);
9521 Rm = Bits32(opcode, 3, 0);
9522 setflags = BitIsSet(opcode, 20);
9523 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9528 Rd = Bits32(opcode, 15, 12);
9529 Rn = Bits32(opcode, 19, 16);
9530 Rm = Bits32(opcode, 3, 0);
9531 setflags = BitIsSet(opcode, 20);
9532 shift_n = DecodeImmShiftARM(opcode, shift_t);
9537 return EmulateSUBSPcLrEtc(opcode, encoding);
9567 bool EmulateInstructionARM::EmulateSUBImmThumb(const uint32_t opcode,
9591 Rd = Bits32(opcode, 2, 0);
9592 Rn = Bits32(opcode, 5, 3);
9594 imm32 = Bits32(opcode, 8, 6); // imm32 = ZeroExtend(imm3, 32)
9597 Rd = Rn = Bits32(opcode, 10, 8);
9599 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
9602 Rd = Bits32(opcode, 11, 8);
9603 Rn = Bits32(opcode, 19, 16);
9604 setflags = BitIsSet(opcode, 20);
9605 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9609 return EmulateCMPImm(opcode, eEncodingT2);
9613 return EmulateSUBSPImm(opcode, eEncodingT2);
9620 Rd = Bits32(opcode, 11, 8);
9621 Rn = Bits32(opcode, 19, 16);
9622 setflags = BitIsSet(opcode, 20);
9623 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
9627 return EmulateADR(opcode, eEncodingT2);
9631 return EmulateSUBSPImm(opcode, eEncodingT3);
9657 bool EmulateInstructionARM::EmulateSUBImmARM(const uint32_t opcode,
9677 if (ConditionPassed(opcode)) {
9685 Rd = Bits32(opcode, 15, 12);
9686 Rn = Bits32(opcode, 19, 16);
9687 setflags = BitIsSet(opcode, 20);
9688 imm32 = ARMExpandImm(opcode); // imm32 = ARMExpandImm(imm12)
9692 return EmulateADR(opcode, eEncodingA2);
9696 return EmulateSUBSPImm(opcode, eEncodingA1);
9701 return EmulateSUBSPcLrEtc(opcode, encoding);
9734 bool EmulateInstructionARM::EmulateTEQImm(const uint32_t opcode,
9749 if (ConditionPassed(opcode)) {
9756 Rn = Bits32(opcode, 19, 16);
9758 opcode, APSR_C,
9764 Rn = Bits32(opcode, 19, 16);
9766 ARMExpandImm_C(opcode, APSR_C,
9793 bool EmulateInstructionARM::EmulateTEQReg(const uint32_t opcode,
9809 if (ConditionPassed(opcode)) {
9816 Rn = Bits32(opcode, 19, 16);
9817 Rm = Bits32(opcode, 3, 0);
9818 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9823 Rn = Bits32(opcode, 19, 16);
9824 Rm = Bits32(opcode, 3, 0);
9825 shift_n = DecodeImmShiftARM(opcode, shift_t);
9859 bool EmulateInstructionARM::EmulateTSTImm(const uint32_t opcode,
9874 if (ConditionPassed(opcode)) {
9881 Rn = Bits32(opcode, 19, 16);
9883 opcode, APSR_C,
9889 Rn = Bits32(opcode, 19, 16);
9891 ARMExpandImm_C(opcode, APSR_C,
9918 bool EmulateInstructionARM::EmulateTSTReg(const uint32_t opcode,
9934 if (ConditionPassed(opcode)) {
9941 Rn = Bits32(opcode, 2, 0);
9942 Rm = Bits32(opcode, 5, 3);
9947 Rn = Bits32(opcode, 19, 16);
9948 Rm = Bits32(opcode, 3, 0);
9949 shift_n = DecodeImmShiftThumb(opcode, shift_t);
9954 Rn = Bits32(opcode, 19, 16);
9955 Rm = Bits32(opcode, 3, 0);
9956 shift_n = DecodeImmShiftARM(opcode, shift_t);
9988 bool EmulateInstructionARM::EmulateSUBSPReg(const uint32_t opcode,
10008 if (ConditionPassed(opcode)) {
10018 d = Bits32(opcode, 11, 8);
10019 m = Bits32(opcode, 3, 0);
10020 setflags = BitIsSet(opcode, 20);
10023 shift_n = DecodeImmShiftThumb(opcode, shift_t);
10037 d = Bits32(opcode, 15, 12);
10038 m = Bits32(opcode, 3, 0);
10039 setflags = BitIsSet(opcode, 20);
10044 EmulateSUBSPcLrEtc(opcode, encoding);
10047 shift_n = DecodeImmShiftARM(opcode, shift_t);
10086 bool EmulateInstructionARM::EmulateADDRegShift(const uint32_t opcode,
10104 if (ConditionPassed(opcode)) {
10115 d = Bits32(opcode, 15, 12);
10116 n = Bits32(opcode, 19, 16);
10117 m = Bits32(opcode, 3, 0);
10118 s = Bits32(opcode, 11, 8);
10121 setflags = BitIsSet(opcode, 20);
10122 shift_t = DecodeRegShift(Bits32(opcode, 6, 5));
10182 bool EmulateInstructionARM::EmulateSUBReg(const uint32_t opcode,
10202 if (ConditionPassed(opcode)) {
10213 d = Bits32(opcode, 2, 0);
10214 n = Bits32(opcode, 5, 3);
10215 m = Bits32(opcode, 8, 6);
10226 d = Bits32(opcode, 11, 8);
10227 n = Bits32(opcode, 19, 16);
10228 m = Bits32(opcode, 3, 0);
10229 setflags = BitIsSet(opcode, 20);
10233 return EmulateCMPImm(opcode, eEncodingT3);
10237 return EmulateSUBSPReg(opcode, eEncodingT1);
10240 shift_n = DecodeImmShiftThumb(opcode, shift_t);
10244 if ((d == 13) || ((d == 15) && BitIsClear(opcode, 20)) || (n == 15) ||
10253 d = Bits32(opcode, 15, 12);
10254 n = Bits32(opcode, 19, 16);
10255 m = Bits32(opcode, 3, 0);
10256 setflags = BitIsSet(opcode, 20);
10261 EmulateSUBSPcLrEtc(opcode, encoding);
10264 shift_n = DecodeImmShiftARM(opcode, shift_t);
10316 bool EmulateInstructionARM::EmulateSTREX(const uint32_t opcode,
10331 if (ConditionPassed(opcode)) {
10343 d = Bits32(opcode, 11, 8);
10344 t = Bits32(opcode, 15, 12);
10345 n = Bits32(opcode, 19, 16);
10346 imm32 = Bits32(opcode, 7, 0) << 2;
10361 d = Bits32(opcode, 15, 12);
10362 t = Bits32(opcode, 3, 0);
10363 n = Bits32(opcode, 19, 16);
10427 bool EmulateInstructionARM::EmulateSTRBImmARM(const uint32_t opcode,
10440 if (ConditionPassed(opcode)) {
10452 t = Bits32(opcode, 15, 12);
10453 n = Bits32(opcode, 19, 16);
10454 imm32 = Bits32(opcode, 11, 0);
10457 index = BitIsSet(opcode, 24);
10458 add = BitIsSet(opcode, 23);
10459 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
10520 bool EmulateInstructionARM::EmulateSTRImmARM(const uint32_t opcode,
10533 if (ConditionPassed(opcode)) {
10549 t = Bits32(opcode, 15, 12);
10550 n = Bits32(opcode, 19, 16);
10551 imm32 = Bits32(opcode, 11, 0);
10554 index = BitIsSet(opcode, 24);
10555 add = BitIsSet(opcode, 23);
10556 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
10629 bool EmulateInstructionARM::EmulateLDRDImmediate(const uint32_t opcode,
10643 if (ConditionPassed(opcode)) {
10658 t = Bits32(opcode, 15, 12);
10659 t2 = Bits32(opcode, 11, 8);
10660 n = Bits32(opcode, 19, 16);
10661 imm32 = Bits32(opcode, 7, 0) << 2;
10664 index = BitIsSet(opcode, 24);
10665 add = BitIsSet(opcode, 23);
10666 wback = BitIsSet(opcode, 21);
10683 t = Bits32(opcode, 15, 12);
10687 n = Bits32(opcode, 19, 16);
10688 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0);
10691 index = BitIsSet(opcode, 24);
10692 add = BitIsSet(opcode, 23);
10693 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
10696 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21))
10775 bool EmulateInstructionARM::EmulateLDRDRegister(const uint32_t opcode,
10789 if (ConditionPassed(opcode)) {
10802 t = Bits32(opcode, 15, 12);
10806 n = Bits32(opcode, 19, 16);
10807 m = Bits32(opcode, 3, 0);
10810 index = BitIsSet(opcode, 24);
10811 add = BitIsSet(opcode, 23);
10812 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
10815 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21))
10900 bool EmulateInstructionARM::EmulateSTRDImm(const uint32_t opcode,
10914 if (ConditionPassed(opcode)) {
10928 t = Bits32(opcode, 15, 12);
10929 t2 = Bits32(opcode, 11, 8);
10930 n = Bits32(opcode, 19, 16);
10931 imm32 = Bits32(opcode, 7, 0) << 2;
10934 index = BitIsSet(opcode, 24);
10935 add = BitIsSet(opcode, 23);
10936 wback = BitIsSet(opcode, 21);
10952 t = Bits32(opcode, 15, 12);
10957 n = Bits32(opcode, 19, 16);
10958 imm32 = (Bits32(opcode, 11, 8) << 4) | Bits32(opcode, 3, 0);
10961 index = BitIsSet(opcode, 24);
10962 add = BitIsSet(opcode, 23);
10963 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
10966 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21))
11053 bool EmulateInstructionARM::EmulateSTRDReg(const uint32_t opcode,
11067 if (ConditionPassed(opcode)) {
11080 t = Bits32(opcode, 15, 12);
11085 n = Bits32(opcode, 19, 16);
11086 m = Bits32(opcode, 3, 0);
11089 index = BitIsSet(opcode, 24);
11090 add = BitIsSet(opcode, 23);
11091 wback = BitIsClear(opcode, 24) || BitIsSet(opcode, 21);
11094 if (BitIsClear(opcode, 24) && BitIsSet(opcode, 21))
11190 bool EmulateInstructionARM::EmulateVLDM(const uint32_t opcode,
11209 if (ConditionPassed(opcode)) {
11225 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21))
11232 add = BitIsSet(opcode, 23);
11233 wback = BitIsSet(opcode, 21);
11236 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
11237 n = Bits32(opcode, 19, 16);
11238 imm32 = Bits32(opcode, 7, 0) << 2;
11241 regs = Bits32(opcode, 7, 0) / 2;
11260 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21))
11268 add = BitIsSet(opcode, 23);
11269 wback = BitIsSet(opcode, 21);
11270 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22);
11271 n = Bits32(opcode, 19, 16);
11274 imm32 = Bits32(opcode, 7, 0) << 2;
11275 regs = Bits32(opcode, 7, 0);
11383 bool EmulateInstructionARM::EmulateVSTM(const uint32_t opcode,
11403 if (ConditionPassed(opcode)) {
11419 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21))
11426 add = BitIsSet(opcode, 23);
11427 wback = BitIsSet(opcode, 21);
11430 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
11431 n = Bits32(opcode, 19, 16);
11432 imm32 = Bits32(opcode, 7, 0) << 2;
11435 regs = Bits32(opcode, 7, 0) / 2;
11454 if ((Bit32(opcode, 24) == Bit32(opcode, 23)) && BitIsSet(opcode, 21))
11462 add = BitIsSet(opcode, 23);
11463 wback = BitIsSet(opcode, 21);
11464 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22);
11465 n = Bits32(opcode, 19, 16);
11468 imm32 = Bits32(opcode, 7, 0) << 2;
11469 regs = Bits32(opcode, 7, 0);
11588 bool EmulateInstructionARM::EmulateVLDR(const uint32_t opcode,
11606 if (ConditionPassed(opcode)) {
11619 add = BitIsSet(opcode, 23);
11620 imm32 = Bits32(opcode, 7, 0) << 2;
11623 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
11624 n = Bits32(opcode, 19, 16);
11632 add = BitIsSet(opcode, 23);
11633 imm32 = Bits32(opcode, 7, 0) << 2;
11636 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22);
11637 n = Bits32(opcode, 19, 16);
11715 bool EmulateInstructionARM::EmulateVSTR(const uint32_t opcode,
11732 if (ConditionPassed(opcode)) {
11745 add = BitIsSet(opcode, 23);
11746 imm32 = Bits32(opcode, 7, 0) << 2;
11749 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
11750 n = Bits32(opcode, 19, 16);
11762 add = BitIsSet(opcode, 23);
11763 imm32 = Bits32(opcode, 7, 0) << 2;
11766 d = (Bits32(opcode, 15, 12) << 1) | Bit32(opcode, 22);
11767 n = Bits32(opcode, 19, 16);
11847 bool EmulateInstructionARM::EmulateVLD1Multiple(const uint32_t opcode,
11862 if (ConditionPassed(opcode)) {
11888 uint32_t type = Bits32(opcode, 11, 8);
11889 uint32_t align = Bits32(opcode, 5, 4);
11919 ebytes = 1 << Bits32(opcode, 7, 6);
11924 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
11925 n = Bits32(opcode, 19, 15);
11926 m = Bits32(opcode, 3, 0);
12005 bool EmulateInstructionARM::EmulateVLD1Single(const uint32_t opcode,
12017 if (ConditionPassed(opcode)) {
12031 uint32_t size = Bits32(opcode, 11, 10);
12032 uint32_t index_align = Bits32(opcode, 7, 4);
12035 return EmulateVLD1SingleAll(opcode, encoding);
12090 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
12091 n = Bits32(opcode, 19, 16);
12092 m = Bits32(opcode, 3, 0);
12181 bool EmulateInstructionARM::EmulateVST1Multiple(const uint32_t opcode,
12196 if (ConditionPassed(opcode)) {
12211 uint32_t type = Bits32(opcode, 11, 8);
12212 uint32_t align = Bits32(opcode, 5, 4);
12247 ebytes = 1 << Bits32(opcode, 7, 6);
12252 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
12253 n = Bits32(opcode, 19, 16);
12254 m = Bits32(opcode, 3, 0);
12337 bool EmulateInstructionARM::EmulateVST1Single(const uint32_t opcode,
12349 if (ConditionPassed(opcode)) {
12363 uint32_t size = Bits32(opcode, 11, 10);
12364 uint32_t index_align = Bits32(opcode, 7, 4);
12423 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
12424 n = Bits32(opcode, 19, 16);
12425 m = Bits32(opcode, 3, 0);
12496 bool EmulateInstructionARM::EmulateVLD1SingleAll(const uint32_t opcode,
12510 if (ConditionPassed(opcode)) {
12525 uint32_t size = Bits32(opcode, 7, 6);
12526 if ((size == 3) || ((size == 0) && BitIsSet(opcode, 4)))
12533 if (BitIsClear(opcode, 5))
12539 if (BitIsClear(opcode, 4))
12545 d = (Bit32(opcode, 22) << 4) | Bits32(opcode, 15, 12);
12546 n = Bits32(opcode, 19, 16);
12547 m = Bits32(opcode, 3, 0);
12626 bool EmulateInstructionARM::EmulateSUBSPcLrEtc(const uint32_t opcode,
12634 case opcode of
12653 if (ConditionPassed(opcode)) {
12665 // imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = '0010';
12668 imm32 = Bits32(opcode, 7, 0);
12680 n = Bits32(opcode, 19, 16);
12681 imm32 = ARMExpandImm(opcode);
12683 code = Bits32(opcode, 24, 21);
12689 n = Bits32(opcode, 19, 16);
12690 m = Bits32(opcode, 3, 0);
12694 shift_n = DecodeImmShiftARM(opcode, shift_t);
12723 // case opcode of
12810 EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
13174 if ((g_arm_opcodes[i].mask & opcode) == g_arm_opcodes[i].value &&
13182 EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
13252 // The next 5 opcode _must_ come before the if then instruction
13724 if ((g_thumb_opcodes[i].mask & opcode) == g_thumb_opcodes[i].value &&
13844 bool EmulateInstructionARM::ConditionPassed(const uint32_t opcode) {
13851 const uint32_t cond = CurrentCond(opcode);
13917 uint32_t EmulateInstructionARM::CurrentCond(const uint32_t opcode) {
13923 return UnsignedBits(opcode, 31, 28);
13931 if (Bits32(opcode, 15, 12) == 0x0d && Bits32(opcode, 11, 8) != 0x0f)
13932 return Bits32(opcode, 11, 8);
13934 if (Bits32(opcode, 31, 27) == 0x1e && Bits32(opcode, 15, 14) == 0x02 &&
13935 Bits32(opcode, 12, 12) == 0x00 && Bits32(opcode, 25, 22) <= 0x0d) {
13936 return Bits32(opcode, 25, 22);
14306 // Call the Emulate... function if we managed to decode the opcode.
14356 static constexpr llvm::StringLiteral opcode_key("opcode");
14365 out_stream.Printf("TestEmulation: Error reading opcode from test file.\n");