Lines Matching defs:imm8
1173 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32)
1388 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
1403 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm4:i:imm3:imm8,
1410 uint32_t imm8 = Bits32(opcode, 7, 0);
1411 imm32 = (imm4 << 12) | (i << 11) | (imm3 << 8) | imm8;
1783 imm32 = Bits32(opcode, 7, 0) << 2; // imm32 = ZeroExtend(imm8:'00', 32);
1858 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(imm8:'00', 32);
1873 // ThumbExpandImm(i:imm3:imm8);
1889 // d = UInt(Rd); setflags = FALSE; imm32 = ZeroExtend(i:imm3:imm8, 32);
1894 uint32_t imm8 = Bits32(opcode, 7, 0);
1895 imm32 = (i << 11) | (imm3 << 8) | imm8;
2409 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
2418 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
2589 // If UInt(imm8) is odd, see "FSTMX".
2681 // If UInt(imm8) is odd, see "FLDMX".
3047 // ZeroExtend(imm8, 32);
3058 // ThumbExpandImm(i:imm3:imm8);
3077 // ZeroExtend(i:imm3:imm8, 32);
3083 uint32_t imm8 = Bits32(opcode, 7, 0);
3084 imm32 = (i << 11) | (imm3 << 8) | imm8;
3305 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
3422 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
4448 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
4481 // if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 ==
4487 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5154 // t = UInt(Rt); n = 13; imm32 = ZeroExtend(imm8:'00', 32);
5187 // if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 ==
5194 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5530 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
5810 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
5956 imm32 = ThumbImm8Scaled(opcode); // imm32 = ZeroExtend(imm8:'00', 32)
5962 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
6030 carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
6195 carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
6735 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7125 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7535 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
7937 // t = UInt(Rt); n = UInt(Rn); imm32 = ZeroExtend(imm8, 32);
8834 carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9003 carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9171 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9445 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9599 imm32 = Bits32(opcode, 7, 0); // imm32 = ZeroExtend(imm8, 32)
9605 imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
9623 imm32 = ThumbImm12(opcode); // imm32 = ZeroExtend(i:imm3:imm8, 32)
9759 carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
9884 carry); // (imm32, carry) = ThumbExpandImm(i:imm3:imm8, APSR.C)
10341 // ZeroExtend(imm8:'00',
10657 // ZeroExtend(imm8:'00', 32);
10927 // ZeroExtend(imm8:'00', 32);
11235 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32);
11240 // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see 'FLDMX'.
11273 // imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8);
11429 // d = UInt(D:Vd); n = UInt(Rn); imm32 = ZeroExtend(imm8:'00', 32);
11434 // regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see 'FSTMX'.
11467 // imm32 = ZeroExtend(imm8:'00', 32); regs = UInt(imm8);
11616 // single_reg = FALSE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00',
11630 // single_reg = TRUE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00', 32);
11742 // single_reg = FALSE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00',
11760 // single_reg = TRUE; add = (U == '1'); imm32 = ZeroExtend(imm8:'00', 32);
12665 // imm32 = ZeroExtend(imm8, 32); register_form = FALSE; opcode = '0010';
13076 "ldrsb<c> <Rt>, [<Rn>{,#+/-<imm8>}]"},
13084 "ldrsh<c> <Rt>,[<Rn>{,#+/-<imm8>}]"},
13092 "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
13139 "strd<c> <Rt>, <Rt2>, [<Rn> #+/-<imm8>]!"},
13249 &EmulateInstructionARM::EmulateSVC, "svc #imm8"},
13267 // To resolve ambiguity, "b<c> #imm8" should come after "svc #imm8".
13269 &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"},
13273 &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"},
13276 "b<c>.w #imm8 (outside or last in IT)"},
13385 &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rdn>,#<imm8>"},
13397 &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rdn>, #imm8"},
13441 &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"},
13465 &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #imm8"},
13527 &EmulateInstructionARM::EmulateSUBSPcLrEtc, "SUBS<c> PC, LR, #<imm8>"},
13554 "ldr<c> <Rt>, [<Rn>{,#+/-<imm8>}]{!}"},
13572 "ldrb<c> <Rt>,[<Rn>, #+/-<imm8>]{!}"},
13588 "ldrh<c> <Rt>,[<Rn>,#+/-<imm8>]{!}"},
13602 "ldrsb<c> <Rt>,[<Rn>,#+/-<imm8>]"},
13616 "ldrsh<c> <Rt>,[<Rn>,#+/-<imm8>]"},
13662 "str<c> <Rt>, [<Rn>,#+/-<imm8>]"},
13676 "strb<c> <Rt> ,[<Rn>, #+/-<imm8>]{!}"},