Lines Matching defs:Rm
1288 uint32_t Rm; // the source register
1294 Rm = Bits32(opcode, 6, 3);
1301 Rm = Bits32(opcode, 5, 3);
1308 Rm = Bits32(opcode, 3, 0);
1311 if (setflags && (BadReg(Rd) || BadReg(Rm)))
1315 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
1320 Rm = Bits32(opcode, 3, 0);
1331 uint32_t result = ReadCoreReg(Rm, &success);
1335 // The context specifies that Rm is to be moved into Rd.
1339 else if (Rd == GetFramePointerRegisterNumber() && Rm == 13)
1344 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
1509 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = FALSE;
1522 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
1680 uint32_t Rm; // the source register
1683 uint32_t shift_n; // the shift applied to the value read from Rm
1689 Rm = Bits32(opcode, 5, 3);
1698 Rm = Bits32(opcode, 3, 0);
1702 if (BadReg(Rd) || BadReg(Rm))
1707 Rm = Bits32(opcode, 3, 0);
1715 uint32_t value = ReadCoreReg(Rm, &success);
1965 uint32_t Rm; // the second operand
1968 Rm = Bits32(opcode, 6, 3);
1973 int32_t reg_value = ReadCoreReg(Rm, &success);
1984 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
2129 uint32_t Rm; // the register with the target address
2133 Rm = Bits32(opcode, 6, 3);
2135 if (Rm == 15)
2142 Rm = Bits32(opcode, 3, 0);
2144 if (Rm == 15)
2150 addr_t target = ReadCoreReg(Rm, &success);
2154 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
2181 uint32_t Rm; // the register with the target address
2184 Rm = Bits32(opcode, 6, 3);
2189 Rm = Bits32(opcode, 3, 0);
2195 addr_t target = ReadCoreReg(Rm, &success);
2200 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
2235 uint32_t Rm; // the register with the target address
2238 Rm = Bits32(opcode, 19, 16);
2239 if (BadReg(Rm))
2245 Rm = Bits32(opcode, 3, 0);
2246 if (Rm == 15)
2253 addr_t target = ReadCoreReg(Rm, &success);
2258 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
2953 uint32_t Rm; // the index register which contains an integer pointing to a
2959 Rm = Bits32(opcode, 3, 0);
2961 if (Rn == 13 || BadReg(Rm))
2977 uint32_t index = ReadCoreReg(Rm, &success);
3218 uint32_t Rd, Rn, Rm;
3220 uint32_t shift_n; // the shift applied to the value read from Rm
3226 Rm = Bits32(opcode, 8, 6);
3233 Rm = Bits32(opcode, 6, 3);
3237 if (Rn == 15 && Rm == 15)
3245 Rm = Bits32(opcode, 3, 0);
3259 uint32_t val2 = ReadCoreReg(Rm, &success);
3273 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rm);
3349 uint32_t Rm; // the second operand
3351 uint32_t shift_n; // the shift applied to the value read from Rm
3355 Rm = Bits32(opcode, 5, 3);
3361 Rm = Bits32(opcode, 3, 0);
3364 if (Rn == 15 || BadReg(Rm))
3369 Rm = Bits32(opcode, 3, 0);
3380 // Read the register value from register Rm.
3381 uint32_t val2 = ReadCoreReg(Rm, &success);
3466 uint32_t Rm; // the second operand
3468 uint32_t shift_n; // the shift applied to the value read from Rm
3472 Rm = Bits32(opcode, 5, 3);
3478 Rm = Bits32(opcode, 6, 3);
3481 if (Rn < 8 && Rm < 8)
3483 if (Rn == 15 || Rm == 15)
3488 Rm = Bits32(opcode, 3, 0);
3490 if (Rn == 15 || BadReg(Rm))
3495 Rm = Bits32(opcode, 3, 0);
3506 // Read the register value from register Rm.
3507 uint32_t val2 = ReadCoreReg(Rm, &success);
3754 uint32_t Rm; // the first operand register
3772 Rm = Bits32(opcode, 5, 3);
3783 Rm = Bits32(opcode, 3, 0);
3786 if (BadReg(Rd) || BadReg(Rm))
3791 Rm = Bits32(opcode, 3, 0);
3804 uint32_t value = ReadCoreReg(Rm, &success);
3841 Rm; // the register whose bottom byte contains the amount to shift by
3848 Rm = Bits32(opcode, 5, 3);
3854 Rm = Bits32(opcode, 3, 0);
3856 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
3862 Rm = Bits32(opcode, 11, 8);
3864 if (Rd == 15 || Rn == 15 || Rm == 15)
3875 // Get the Rm register content.
3876 uint32_t val = ReadCoreReg(Rm, &success);
5319 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5339 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5360 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5638 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5656 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5680 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
5709 uint32_t Rm = ReadCoreReg(m, &success);
5718 uint32_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
5871 uint32_t Rd, Rn, Rm;
5873 uint32_t shift_n; // the shift applied to the value read from Rm
5878 Rm = Bits32(opcode, 5, 3);
5886 Rm = Bits32(opcode, 3, 0);
5889 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
5895 Rm = Bits32(opcode, 3, 0);
5912 int32_t val2 = ReadCoreReg(Rm, &success);
6094 uint32_t Rd, Rn, Rm;
6096 uint32_t shift_n; // the shift applied to the value read from Rm
6102 Rm = Bits32(opcode, 5, 3);
6110 Rm = Bits32(opcode, 3, 0);
6116 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
6122 Rm = Bits32(opcode, 3, 0);
6139 uint32_t val2 = ReadCoreReg(Rm, &success);
6259 uint32_t Rd, Rn, Rm;
6261 uint32_t shift_n; // the shift applied to the value read from Rm
6267 Rm = Bits32(opcode, 5, 3);
6275 Rm = Bits32(opcode, 3, 0);
6278 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
6284 Rm = Bits32(opcode, 3, 0);
6303 uint32_t val2 = ReadCoreReg(Rm, &success);
6501 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6519 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6545 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6574 uint32_t Rm =
6590 Shift(Rm, shift_t, shift_n, Bit32(m_opcode_cpsr, APSR_C), &success);
6923 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6939 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
6968 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7001 uint32_t Rm =
7006 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
7342 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7361 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7382 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7413 uint64_t Rm =
7418 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
7749 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7768 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7789 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
7817 uint64_t Rm =
7823 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
8175 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
8194 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
8216 // t = UInt(Rt); n = UInt(Rn); m = UInt(Rm);
8245 uint64_t Rm =
8256 addr_t offset = Shift(Rm, shift_t, shift_n, APSR_C, &success);
8340 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8348 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8360 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8375 uint64_t Rm =
8381 uint64_t rotated = ROR(Rm, rotation, &success);
8425 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8433 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8445 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8460 uint64_t Rm =
8466 uint64_t rotated = ROR(Rm, rotation, &success);
8510 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8518 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8530 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8545 uint64_t Rm =
8551 uint64_t rotated = ROR(Rm, rotation, &success);
8592 // d = UInt(Rd); m = UInt(Rm); rotation = 0;
8600 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8612 // d = UInt(Rd); m = UInt(Rm); rotation = UInt(rotate:'000');
8627 uint64_t Rm =
8633 uint64_t rotated = ROR(Rm, rotation, &success);
8901 uint32_t Rd, Rn, Rm;
8903 uint32_t shift_n; // the shift applied to the value read from Rm
8909 Rm = Bits32(opcode, 5, 3);
8917 Rm = Bits32(opcode, 3, 0);
8923 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn) || BadReg(Rm))
8929 Rm = Bits32(opcode, 3, 0);
8948 uint32_t val2 = ReadCoreReg(Rm, &success);
9068 uint32_t Rd, Rn, Rm;
9070 uint32_t shift_n; // the shift applied to the value read from Rm
9076 Rm = Bits32(opcode, 5, 3);
9084 Rm = Bits32(opcode, 3, 0);
9090 if (BadReg(Rd) || Rn == 13 || BadReg(Rm))
9096 Rm = Bits32(opcode, 3, 0);
9113 uint32_t val2 = ReadCoreReg(Rm, &success);
9230 uint32_t Rm; // the second operand
9233 uint32_t shift_n; // the shift applied to the value read from Rm
9238 Rm = Bits32(opcode, 3, 0);
9242 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
9248 Rm = Bits32(opcode, 3, 0);
9265 // Read the register value from register Rm.
9266 uint32_t val2 = ReadCoreReg(Rm, &success);
9368 uint32_t Rm; // the second operand
9371 uint32_t shift_n; // the shift applied to the value read from Rm
9376 Rm = Bits32(opcode, 3, 0);
9393 // Read the register value from register Rm.
9394 uint32_t val2 = ReadCoreReg(Rm, &success);
9506 uint32_t Rm; // the second operand
9509 uint32_t shift_n; // the shift applied to the value read from Rm
9513 Rm = Bits32(opcode, 5, 3);
9521 Rm = Bits32(opcode, 3, 0);
9524 if (BadReg(Rd) || BadReg(Rn) || BadReg(Rm))
9530 Rm = Bits32(opcode, 3, 0);
9547 // Read the register value from register Rm.
9548 uint32_t val2 = ReadCoreReg(Rm, &success);
9810 uint32_t Rn, Rm;
9812 uint32_t shift_n; // the shift applied to the value read from Rm
9817 Rm = Bits32(opcode, 3, 0);
9819 if (BadReg(Rn) || BadReg(Rm))
9824 Rm = Bits32(opcode, 3, 0);
9837 uint32_t val2 = ReadCoreReg(Rm, &success);
9935 uint32_t Rn, Rm;
9937 uint32_t shift_n; // the shift applied to the value read from Rm
9942 Rm = Bits32(opcode, 5, 3);
9948 Rm = Bits32(opcode, 3, 0);
9950 if (BadReg(Rn) || BadReg(Rm))
9955 Rm = Bits32(opcode, 3, 0);
9968 uint32_t val2 = ReadCoreReg(Rm, &success);
10017 // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1');
10036 // d = UInt(Rd); m = UInt(Rm); setflags = (S == '1');
10055 uint32_t Rm = ReadCoreReg(m, &success);
10059 uint32_t shifted = Shift(Rm, shift_t, shift_n, APSR_C, &success);
10114 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); s = UInt(Rs);
10141 uint32_t Rm = ReadCoreReg(m, &success);
10145 uint32_t shifted = Shift(Rm, shift_t, shift_n, APSR_C, &success);
10212 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = !InITBlock();
10225 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S =="1");
10252 // d = UInt(Rd); n = UInt(Rn); m = UInt(Rm); setflags = (S == '1');
10273 uint32_t Rm = ReadCoreReg(m, &success);
10277 uint32_t shifted = Shift(Rm, shift_t, shift_n, APSR_C, &success);
10801 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
10839 uint32_t Rm = ReadCoreReg(m, &success);
10846 offset_addr = Rn + Rm;
10848 offset_addr = Rn - Rm;
11079 // t = UInt(Rt); t2 = t+1; n = UInt(Rn); m = UInt(Rm);
11119 uint32_t Rm = ReadCoreReg(m, &success);
11126 offset_addr = Rn + Rm;
11128 offset_addr = Rn - Rm;
11923 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
11957 uint32_t Rm = ReadCoreReg(m, &success);
11963 offset = Rm;
12089 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
12121 uint32_t Rm = ReadCoreReg(m, &success);
12127 offset = Rm;
12251 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
12289 uint32_t Rm = ReadCoreReg(m, &success);
12295 offset = Rm;
12422 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
12456 uint32_t Rm = ReadCoreReg(m, &success);
12462 offset = Rm;
12544 // d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
12578 uint32_t Rm = ReadCoreReg(m, &success);
12584 offset = Rm;
12688 // n = UInt(Rn); m = UInt(Rm); register_form = TRUE;
12706 uint32_t Rm = ReadCoreReg(m, &success);
12710 operand2 = Shift(Rm, shift_t, shift_n, APSR_C, &success);
12839 "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}"},
12877 &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12880 &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12883 &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12892 "adc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12900 "add{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12904 "add{s}<c> <Rd>, <Rn>, <Rm>, <type> <RS>"},
12916 "and{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12923 "bic{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12930 "eor{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12937 "orr{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12944 "rsb{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12951 "rsc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12958 "sbc{s}<c> <Rd>, <Rn>, <Rm> {,<shift>}"},
12969 "sub{s}<c> <Rd>, <Rn>, <Rm>{,<shift>}"},
12975 &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12981 &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rn>, <Rm> {,<shift>}"},
12990 &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
12997 "mvn{s}<c> <Rd>, <Rm> {,<shift>}"},
13003 &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
13009 &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm> {,<shift>}"},
13012 &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
13015 &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
13018 &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
13021 &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
13024 &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
13027 &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
13030 &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
13033 &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
13036 &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
13039 &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>"},
13047 "<opc>S<c> PC,<Rn>,<Rm{,<shift>}"},
13063 "ldr<c> <Rt> [<Rn> +/-<Rm> {<shift>}] {!}"},
13068 "ldrb<c> <Rt>, [<Rn>,+/-<Rm>{, <shift>}]{!}"},
13073 "ldrh<c> <Rt>,[<Rn>,+/-<Rm>]{!}"},
13081 "ldrsb<c> <Rt>,[<Rn>,+/-<Rm>]{!}"},
13089 "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}"},
13095 "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
13106 "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13109 "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13112 "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13125 "str<c> <Rt> [<Rn> +/-<Rm> {<shift>}]{!}"},
13128 "strh<c> <Rt>,[<Rn>,+/-<Rm>[{!}"},
13142 "strd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
13153 "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13156 "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13160 &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}"},
13162 &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}"},
13164 &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}"},
13166 &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}"},
13213 &EmulateInstructionARM::EmulateADDSPRm, "add sp, <Rm>"},
13222 "sub{s}<c> <Rd>, sp, <Rm>{,<shift>}"},
13284 &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
13287 &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
13290 &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
13296 &EmulateInstructionARM::EmulateTB, "tbb<c> <Rn>, <Rm>"},
13299 &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"},
13307 &EmulateInstructionARM::EmulateADCReg, "adcs|adc<c> <Rdn>, <Rm>"},
13310 "adc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13313 &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
13314 // Make sure "add sp, <Rm>" comes before this instruction, so there's no
13317 &EmulateInstructionARM::EmulateADDReg, "add<c> <Rdn>, <Rm>"},
13330 &EmulateInstructionARM::EmulateANDReg, "ands|and<c> <Rdn>, <Rm>"},
13333 "and{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13339 &EmulateInstructionARM::EmulateBICReg, "bics|bic<c> <Rdn>, <Rm>"},
13342 "bic{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13348 &EmulateInstructionARM::EmulateEORReg, "eors|eor<c> <Rdn>, <Rm>"},
13351 "eor{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13357 &EmulateInstructionARM::EmulateORRReg, "orrs|orr<c> <Rdn>, <Rm>"},
13360 "orr{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13370 "rsb{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13376 &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc<c> <Rdn>, <Rm>"},
13379 "sbc{s}<c>.w <Rd>, <Rn>, <Rm> {,<shift>}"},
13411 &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
13414 "sub{s}<c>.w <Rd>, <Rn>, <Rm>{,<shift>}"},
13420 &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
13426 &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rdn>, <Rm>"},
13428 &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"},
13432 &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
13435 &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
13436 // mov{s}<c>.w <Rd>, <Rm>
13438 &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
13451 &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
13454 "mvn{s}<c>.w <Rd>, <Rm> {,<shift>}"},
13460 &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm>"},
13462 &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
13468 // cmp (register) (Rn and Rm both from r0-r7)
13470 &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
13471 // cmp (register) (Rn and Rm not both from r0-r7)
13473 &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
13476 "cmp<c>.w <Rn>, <Rm> {, <shift>}"},
13479 &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
13481 &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
13484 &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"},
13486 &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13489 &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
13491 &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
13494 &EmulateInstructionARM::EmulateLSLReg, "lsls|lsl<c> <Rdn>, <Rm>"},
13496 &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
13499 &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
13501 &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
13504 &EmulateInstructionARM::EmulateLSRReg, "lsrs|lsr<c> <Rdn>, <Rm>"},
13506 &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13509 &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
13512 &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
13515 &EmulateInstructionARM::EmulateRORReg, "rors|ror<c> <Rdn>, <Rm>"},
13517 &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
13523 &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>"},
13560 &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]"},
13563 "ldr<c>.w <Rt>, [<Rn>,<Rm>{,LSL #<imm2>}]"},
13576 &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]"},
13579 "ldrb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]"},
13593 "ldrh<c> <Rt>, [<Rn>,<Rm>]"},
13596 "ldrh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]"},
13607 "ldrsb<c> <Rt>,[<Rn>,<Rm>]"},
13610 "ldrsb<c>.w <Rt>,[<Rn>,<Rm>{,LSL #imm2>}]"},
13621 "ldrsh<c> <Rt>,[<Rn>,<Rm>]"},
13624 "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]"},
13638 "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
13641 "vld1<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
13644 "vld1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13664 &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]"},
13667 "str<c>.w <Rt>, [<Rn>, <Rm> {lsl #imm2>}]"},
13678 &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]"},
13681 "strh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]"},
13698 "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13701 "vst1<c>.<size> <list>, [<Rn>{@<align>}], <Rm>"},
13705 &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>"},
13707 &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13709 &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>"},
13711 &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}"},
13713 &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>"},
13715 &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13717 &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>"},
13719 &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}"},