Lines Matching defs:EmulateInstructionARM
1 //===-- EmulateInstructionARM.cpp -----------------------------------------===//
12 #include "EmulateInstructionARM.h"
33 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionARM, InstructionARM)
705 // EmulateInstructionARM implementation
708 void EmulateInstructionARM::Initialize() {
713 void EmulateInstructionARM::Terminate() {
717 llvm::StringRef EmulateInstructionARM::GetPluginDescriptionStatic() {
722 EmulateInstructionARM::CreateInstance(const ArchSpec &arch,
724 if (EmulateInstructionARM::SupportsEmulatingInstructionsOfTypeStatic(
727 std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
728 new EmulateInstructionARM(arch));
733 std::unique_ptr<EmulateInstructionARM> emulate_insn_up(
734 new EmulateInstructionARM(arch));
744 bool EmulateInstructionARM::SetTargetTriple(const ArchSpec &arch) {
755 bool EmulateInstructionARM::WriteBits32UnknownToMemory(addr_t address) {
768 bool EmulateInstructionARM::WriteBits32Unknown(int n) {
787 EmulateInstructionARM::GetRegisterInfo(lldb::RegisterKind reg_kind,
821 uint32_t EmulateInstructionARM::GetFramePointerRegisterNumber() const {
857 uint32_t EmulateInstructionARM::GetFramePointerDWARFRegisterNumber() const {
891 bool EmulateInstructionARM::EmulatePUSH(const uint32_t opcode,
1014 bool EmulateInstructionARM::EmulatePOP(const uint32_t opcode,
1142 bool EmulateInstructionARM::EmulateADDRdSPImm(const uint32_t opcode,
1203 bool EmulateInstructionARM::EmulateMOVRdSP(const uint32_t opcode,
1258 bool EmulateInstructionARM::EmulateMOVLowHigh(const uint32_t opcode,
1265 bool EmulateInstructionARM::EmulateMOVRdRm(const uint32_t opcode,
1356 bool EmulateInstructionARM::EmulateMOVRdImm(const uint32_t opcode,
1469 bool EmulateInstructionARM::EmulateMUL(const uint32_t opcode,
1598 bool EmulateInstructionARM::EmulateMVNImm(const uint32_t opcode,
1658 bool EmulateInstructionARM::EmulateMVNReg(const uint32_t opcode,
1739 bool EmulateInstructionARM::EmulateLDRRtPCRelative(const uint32_t opcode,
1827 bool EmulateInstructionARM::EmulateADDSPImm(const uint32_t opcode,
1938 bool EmulateInstructionARM::EmulateADDSPRm(const uint32_t opcode,
1998 bool EmulateInstructionARM::EmulateBLXImmediate(const uint32_t opcode,
2102 bool EmulateInstructionARM::EmulateBLXRm(const uint32_t opcode,
2167 bool EmulateInstructionARM::EmulateBXRm(const uint32_t opcode,
2215 bool EmulateInstructionARM::EmulateBXJRm(const uint32_t opcode,
2268 bool EmulateInstructionARM::EmulateSUBR7IPImm(const uint32_t opcode,
2318 bool EmulateInstructionARM::EmulateSUBIPSPImm(const uint32_t opcode,
2371 bool EmulateInstructionARM::EmulateSUBSPImm(const uint32_t opcode,
2457 bool EmulateInstructionARM::EmulateSTRRtSP(const uint32_t opcode,
2551 bool EmulateInstructionARM::EmulateVPUSH(const uint32_t opcode,
2644 bool EmulateInstructionARM::EmulateVPOP(const uint32_t opcode,
2733 bool EmulateInstructionARM::EmulateSVC(const uint32_t opcode,
2779 bool EmulateInstructionARM::EmulateIT(const uint32_t opcode,
2791 bool EmulateInstructionARM::EmulateNop(const uint32_t opcode,
2798 bool EmulateInstructionARM::EmulateB(const uint32_t opcode,
2821 // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2832 // The 'cond' field is handled in EmulateInstructionARM::CurrentCond().
2882 bool EmulateInstructionARM::EmulateCB(const uint32_t opcode,
2936 bool EmulateInstructionARM::EmulateTB(const uint32_t opcode,
3010 bool EmulateInstructionARM::EmulateADDImmThumb(const uint32_t opcode,
3131 bool EmulateInstructionARM::EmulateADDImmARM(const uint32_t opcode,
3196 bool EmulateInstructionARM::EmulateADDReg(const uint32_t opcode,
3285 bool EmulateInstructionARM::EmulateCMNImm(const uint32_t opcode,
3332 bool EmulateInstructionARM::EmulateCMNReg(const uint32_t opcode,
3398 bool EmulateInstructionARM::EmulateCMPImm(const uint32_t opcode,
3449 bool EmulateInstructionARM::EmulateCMPReg(const uint32_t opcode,
3526 bool EmulateInstructionARM::EmulateASRImm(const uint32_t opcode,
3552 bool EmulateInstructionARM::EmulateASRReg(const uint32_t opcode,
3574 bool EmulateInstructionARM::EmulateLSLImm(const uint32_t opcode,
3599 bool EmulateInstructionARM::EmulateLSLReg(const uint32_t opcode,
3622 bool EmulateInstructionARM::EmulateLSRImm(const uint32_t opcode,
3647 bool EmulateInstructionARM::EmulateLSRReg(const uint32_t opcode,
3670 bool EmulateInstructionARM::EmulateRORImm(const uint32_t opcode,
3696 bool EmulateInstructionARM::EmulateRORReg(const uint32_t opcode,
3720 bool EmulateInstructionARM::EmulateRRX(const uint32_t opcode,
3741 bool EmulateInstructionARM::EmulateShiftImm(const uint32_t opcode,
3827 bool EmulateInstructionARM::EmulateShiftReg(const uint32_t opcode,
3901 bool EmulateInstructionARM::EmulateLDM(const uint32_t opcode,
4044 bool EmulateInstructionARM::EmulateLDMDA(const uint32_t opcode,
4159 bool EmulateInstructionARM::EmulateLDMDB(const uint32_t opcode,
4296 bool EmulateInstructionARM::EmulateLDMIB(const uint32_t opcode,
4406 bool EmulateInstructionARM::EmulateLDRRtRnImm(const uint32_t opcode,
4569 bool EmulateInstructionARM::EmulateSTM(const uint32_t opcode,
4721 bool EmulateInstructionARM::EmulateSTMDA(const uint32_t opcode,
4843 bool EmulateInstructionARM::EmulateSTMDB(const uint32_t opcode,
4992 bool EmulateInstructionARM::EmulateSTMIB(const uint32_t opcode,
5114 bool EmulateInstructionARM::EmulateSTRThumb(const uint32_t opcode,
5281 bool EmulateInstructionARM::EmulateSTRRegister(const uint32_t opcode,
5470 bool EmulateInstructionARM::EmulateSTRBThumb(const uint32_t opcode,
5606 bool EmulateInstructionARM::EmulateSTRHRegister(const uint32_t opcode,
5780 bool EmulateInstructionARM::EmulateADCImm(const uint32_t opcode,
5849 bool EmulateInstructionARM::EmulateADCReg(const uint32_t opcode,
5934 bool EmulateInstructionARM::EmulateADR(const uint32_t opcode,
5997 bool EmulateInstructionARM::EmulateANDImm(const uint32_t opcode,
6072 bool EmulateInstructionARM::EmulateANDReg(const uint32_t opcode,
6162 bool EmulateInstructionARM::EmulateBICImm(const uint32_t opcode,
6237 bool EmulateInstructionARM::EmulateBICReg(const uint32_t opcode,
6326 bool EmulateInstructionARM::EmulateLDRImmediateARM(const uint32_t opcode,
6462 bool EmulateInstructionARM::EmulateLDRRegister(const uint32_t opcode,
6668 bool EmulateInstructionARM::EmulateLDRBImmediate(const uint32_t opcode,
6815 bool EmulateInstructionARM::EmulateLDRBLiteral(const uint32_t opcode,
6896 bool EmulateInstructionARM::EmulateLDRBRegister(const uint32_t opcode,
7058 bool EmulateInstructionARM::EmulateLDRHImmediate(const uint32_t opcode,
7205 bool EmulateInstructionARM::EmulateLDRHLiteral(const uint32_t opcode,
7309 bool EmulateInstructionARM::EmulateLDRHRegister(const uint32_t opcode,
7485 bool EmulateInstructionARM::EmulateLDRSBImmediate(const uint32_t opcode,
7634 bool EmulateInstructionARM::EmulateLDRSBLiteral(const uint32_t opcode,
7722 bool EmulateInstructionARM::EmulateLDRSBRegister(const uint32_t opcode,
7882 bool EmulateInstructionARM::EmulateLDRSHImmediate(const uint32_t opcode,
8041 bool EmulateInstructionARM::EmulateLDRSHLiteral(const uint32_t opcode,
8142 bool EmulateInstructionARM::EmulateLDRSHRegister(const uint32_t opcode,
8321 bool EmulateInstructionARM::EmulateSXTB(const uint32_t opcode,
8406 bool EmulateInstructionARM::EmulateSXTH(const uint32_t opcode,
8491 bool EmulateInstructionARM::EmulateUXTB(const uint32_t opcode,
8574 bool EmulateInstructionARM::EmulateUXTH(const uint32_t opcode,
8655 bool EmulateInstructionARM::EmulateRFE(const uint32_t opcode,
8801 bool EmulateInstructionARM::EmulateEORImm(const uint32_t opcode,
8879 bool EmulateInstructionARM::EmulateEORReg(const uint32_t opcode,
8970 bool EmulateInstructionARM::EmulateORRImm(const uint32_t opcode,
9046 bool EmulateInstructionARM::EmulateORRReg(const uint32_t opcode,
9135 bool EmulateInstructionARM::EmulateRSBImm(const uint32_t opcode,
9207 bool EmulateInstructionARM::EmulateRSBReg(const uint32_t opcode,
9286 bool EmulateInstructionARM::EmulateRSCImm(const uint32_t opcode,
9345 bool EmulateInstructionARM::EmulateRSCReg(const uint32_t opcode,
9415 bool EmulateInstructionARM::EmulateSBCImm(const uint32_t opcode,
9483 bool EmulateInstructionARM::EmulateSBCReg(const uint32_t opcode,
9567 bool EmulateInstructionARM::EmulateSUBImmThumb(const uint32_t opcode,
9657 bool EmulateInstructionARM::EmulateSUBImmARM(const uint32_t opcode,
9734 bool EmulateInstructionARM::EmulateTEQImm(const uint32_t opcode,
9793 bool EmulateInstructionARM::EmulateTEQReg(const uint32_t opcode,
9859 bool EmulateInstructionARM::EmulateTSTImm(const uint32_t opcode,
9918 bool EmulateInstructionARM::EmulateTSTReg(const uint32_t opcode,
9988 bool EmulateInstructionARM::EmulateSUBSPReg(const uint32_t opcode,
10086 bool EmulateInstructionARM::EmulateADDRegShift(const uint32_t opcode,
10182 bool EmulateInstructionARM::EmulateSUBReg(const uint32_t opcode,
10316 bool EmulateInstructionARM::EmulateSTREX(const uint32_t opcode,
10427 bool EmulateInstructionARM::EmulateSTRBImmARM(const uint32_t opcode,
10520 bool EmulateInstructionARM::EmulateSTRImmARM(const uint32_t opcode,
10629 bool EmulateInstructionARM::EmulateLDRDImmediate(const uint32_t opcode,
10775 bool EmulateInstructionARM::EmulateLDRDRegister(const uint32_t opcode,
10900 bool EmulateInstructionARM::EmulateSTRDImm(const uint32_t opcode,
11053 bool EmulateInstructionARM::EmulateSTRDReg(const uint32_t opcode,
11190 bool EmulateInstructionARM::EmulateVLDM(const uint32_t opcode,
11383 bool EmulateInstructionARM::EmulateVSTM(const uint32_t opcode,
11588 bool EmulateInstructionARM::EmulateVLDR(const uint32_t opcode,
11715 bool EmulateInstructionARM::EmulateVSTR(const uint32_t opcode,
11847 bool EmulateInstructionARM::EmulateVLD1Multiple(const uint32_t opcode,
12005 bool EmulateInstructionARM::EmulateVLD1Single(const uint32_t opcode,
12181 bool EmulateInstructionARM::EmulateVST1Multiple(const uint32_t opcode,
12337 bool EmulateInstructionARM::EmulateVST1Single(const uint32_t opcode,
12496 bool EmulateInstructionARM::EmulateVLD1SingleAll(const uint32_t opcode,
12626 bool EmulateInstructionARM::EmulateSUBSPcLrEtc(const uint32_t opcode,
12809 EmulateInstructionARM::ARMOpcode *
12810 EmulateInstructionARM::GetARMOpcodeForInstruction(const uint32_t opcode,
12817 &EmulateInstructionARM::EmulatePUSH, "push <registers>"},
12819 &EmulateInstructionARM::EmulatePUSH, "push <register>"},
12823 &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #<const>"},
12825 &EmulateInstructionARM::EmulateSUBR7IPImm, "sub r7, ip, #<const>"},
12828 &EmulateInstructionARM::EmulateMOVRdSP, "mov ip, sp"},
12830 &EmulateInstructionARM::EmulateADDRdSPImm, "add ip, sp, #<const>"},
12832 &EmulateInstructionARM::EmulateSUBIPSPImm, "sub ip, sp, #<const>"},
12836 &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #<const>"},
12838 &EmulateInstructionARM::EmulateSUBSPReg,
12844 &EmulateInstructionARM::EmulateSTRRtSP, "str Rt, [sp, #-imm12]!"},
12848 &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"},
12850 &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
12855 &EmulateInstructionARM::EmulatePOP, "pop <registers>"},
12857 &EmulateInstructionARM::EmulatePOP, "pop <register>"},
12859 &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"},
12861 &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
12865 &EmulateInstructionARM::EmulateSVC, "svc #imm24"},
12871 &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"},
12873 &EmulateInstructionARM::EmulateB, "b #imm24"},
12875 &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"},
12877 &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
12880 &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
12883 &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
12888 &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #const"},
12891 &EmulateInstructionARM::EmulateADCReg,
12895 &EmulateInstructionARM::EmulateADDImmARM,
12899 &EmulateInstructionARM::EmulateADDReg,
12903 &EmulateInstructionARM::EmulateADDRegShift,
12907 &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
12909 &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
12912 &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #const"},
12915 &EmulateInstructionARM::EmulateANDReg,
12919 &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #const"},
12922 &EmulateInstructionARM::EmulateBICReg,
12926 &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #const"},
12929 &EmulateInstructionARM::EmulateEORReg,
12933 &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #const"},
12936 &EmulateInstructionARM::EmulateORRReg,
12940 &EmulateInstructionARM::EmulateRSBImm, "rsb{s}<c> <Rd>, <Rn>, #<const>"},
12943 &EmulateInstructionARM::EmulateRSBReg,
12947 &EmulateInstructionARM::EmulateRSCImm, "rsc{s}<c> <Rd>, <Rn>, #<const>"},
12950 &EmulateInstructionARM::EmulateRSCReg,
12954 &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
12957 &EmulateInstructionARM::EmulateSBCReg,
12961 &EmulateInstructionARM::EmulateSUBImmARM,
12965 &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}<c> <Rd>, sp, #<const>"},
12968 &EmulateInstructionARM::EmulateSUBReg,
12972 &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #const"},
12975 &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
12978 &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #const"},
12981 &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rn>, <Rm> {,<shift>}"},
12985 &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c> <Rd>, #<const>"},
12987 &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>, #<imm16>"},
12990 &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c> <Rd>, <Rm>"},
12993 &EmulateInstructionARM::EmulateMVNImm, "mvn{s}<c> <Rd>, #<const>"},
12996 &EmulateInstructionARM::EmulateMVNReg,
13000 &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
13003 &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
13006 &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #<const>"},
13009 &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm> {,<shift>}"},
13012 &EmulateInstructionARM::EmulateASRImm, "asr{s}<c> <Rd>, <Rm>, #imm"},
13015 &EmulateInstructionARM::EmulateASRReg, "asr{s}<c> <Rd>, <Rn>, <Rm>"},
13018 &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c> <Rd>, <Rm>, #imm"},
13021 &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c> <Rd>, <Rn>, <Rm>"},
13024 &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c> <Rd>, <Rm>, #imm"},
13027 &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c> <Rd>, <Rn>, <Rm>"},
13030 &EmulateInstructionARM::EmulateRRX, "rrx{s}<c> <Rd>, <Rm>"},
13033 &EmulateInstructionARM::EmulateRORImm, "ror{s}<c> <Rd>, <Rm>, #imm"},
13036 &EmulateInstructionARM::EmulateRORReg, "ror{s}<c> <Rd>, <Rn>, <Rm>"},
13039 &EmulateInstructionARM::EmulateMUL, "mul{s}<c> <Rd>,<R>,<Rm>"},
13043 &EmulateInstructionARM::EmulateSUBSPcLrEtc,
13046 &EmulateInstructionARM::EmulateSUBSPcLrEtc,
13051 &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>"},
13053 &EmulateInstructionARM::EmulateLDMDA, "ldmda<c> <Rn>{!} <registers>"},
13055 &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>"},
13057 &EmulateInstructionARM::EmulateLDMIB, "ldmib<c> <Rn<{!} <registers>"},
13059 &EmulateInstructionARM::EmulateLDRImmediateARM,
13062 &EmulateInstructionARM::EmulateLDRRegister,
13065 &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>, [...]"},
13067 &EmulateInstructionARM::EmulateLDRBRegister,
13070 &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>"},
13072 &EmulateInstructionARM::EmulateLDRHRegister,
13075 &EmulateInstructionARM::EmulateLDRSBImmediate,
13078 &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt> <label>"},
13080 &EmulateInstructionARM::EmulateLDRSBRegister,
13083 &EmulateInstructionARM::EmulateLDRSHImmediate,
13086 &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>"},
13088 &EmulateInstructionARM::EmulateLDRSHRegister,
13091 &EmulateInstructionARM::EmulateLDRDImmediate,
13094 &EmulateInstructionARM::EmulateLDRDRegister,
13097 &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
13099 &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
13101 &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
13103 &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
13105 &EmulateInstructionARM::EmulateVLD1Multiple,
13108 &EmulateInstructionARM::EmulateVLD1Single,
13111 &EmulateInstructionARM::EmulateVLD1SingleAll,
13116 &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>"},
13118 &EmulateInstructionARM::EmulateSTMDA, "stmda<c> <Rn>{!} <registers>"},
13120 &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>"},
13122 &EmulateInstructionARM::EmulateSTMIB, "stmib<c> <Rn>{!} <registers>"},
13124 &EmulateInstructionARM::EmulateSTRRegister,
13127 &EmulateInstructionARM::EmulateSTRHRegister,
13130 &EmulateInstructionARM::EmulateSTREX, "strex<c> <Rd>, <Rt>, [<Rn>]"},
13132 &EmulateInstructionARM::EmulateSTRBImmARM,
13135 &EmulateInstructionARM::EmulateSTRImmARM,
13138 &EmulateInstructionARM::EmulateSTRDImm,
13141 &EmulateInstructionARM::EmulateSTRDReg,
13144 &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
13146 &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!} <list>"},
13148 &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd> [<Rn>{,#+/-<imm>}]"},
13150 &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd> [<Rn>{,#+/-<imm>}]"},
13152 &EmulateInstructionARM::EmulateVST1Multiple,
13155 &EmulateInstructionARM::EmulateVST1Single,
13160 &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>{,<rotation>}"},
13162 &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>{,<rotation>}"},
13164 &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>{,<rotation>}"},
13166 &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>{,<rotation>}"},
13168 &EmulateInstructionARM::EmulateRFE, "rfe{<amode>} <Rn>{!}"}
13181 EmulateInstructionARM::ARMOpcode *
13182 EmulateInstructionARM::GetThumbOpcodeForInstruction(const uint32_t opcode,
13190 &EmulateInstructionARM::EmulatePUSH, "push <registers>"},
13192 &EmulateInstructionARM::EmulatePUSH, "push.w <registers>"},
13194 &EmulateInstructionARM::EmulatePUSH, "push.w <register>"},
13198 &EmulateInstructionARM::EmulateADDRdSPImm, "add r7, sp, #imm"},
13201 &EmulateInstructionARM::EmulateMOVRdSP, "mov r7, sp"},
13205 &EmulateInstructionARM::EmulateMOVLowHigh, "mov r0-r7, r8-r15"},
13209 &EmulateInstructionARM::EmulateLDRRtPCRelative, "ldr <Rt>, [PC, #imm]"},
13213 &EmulateInstructionARM::EmulateADDSPRm, "add sp, <Rm>"},
13215 &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #imm"},
13217 &EmulateInstructionARM::EmulateSUBSPImm, "sub.w sp, sp, #<const>"},
13219 &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"},
13221 &EmulateInstructionARM::EmulateSUBSPReg,
13226 &EmulateInstructionARM::EmulateVPUSH, "vpush.64 <list>"},
13228 &EmulateInstructionARM::EmulateVPUSH, "vpush.32 <list>"},
13233 &EmulateInstructionARM::EmulateADDSPImm, "add<c> <Rd>, sp, #imm"},
13235 &EmulateInstructionARM::EmulateADDSPImm, "add sp, #imm"},
13237 &EmulateInstructionARM::EmulatePOP, "pop <registers>"},
13239 &EmulateInstructionARM::EmulatePOP, "pop.w <registers>"},
13241 &EmulateInstructionARM::EmulatePOP, "pop.w <register>"},
13243 &EmulateInstructionARM::EmulateVPOP, "vpop.64 <list>"},
13245 &EmulateInstructionARM::EmulateVPOP, "vpop.32 <list>"},
13249 &EmulateInstructionARM::EmulateSVC, "svc #imm8"},
13254 &EmulateInstructionARM::EmulateNop, "nop"},
13256 &EmulateInstructionARM::EmulateNop, "nop YIELD (yield hint)"},
13258 &EmulateInstructionARM::EmulateNop, "nop WFE (wait for event hint)"},
13260 &EmulateInstructionARM::EmulateNop, "nop WFI (wait for interrupt hint)"},
13262 &EmulateInstructionARM::EmulateNop, "nop SEV (send event hint)"},
13264 &EmulateInstructionARM::EmulateIT, "it{<x>{<y>{<z>}}} <firstcond>"},
13269 &EmulateInstructionARM::EmulateB, "b<c> #imm8 (outside IT)"},
13271 &EmulateInstructionARM::EmulateB, "b<c> #imm11 (outside or last in IT)"},
13273 &EmulateInstructionARM::EmulateB, "b<c>.w #imm8 (outside IT)"},
13275 &EmulateInstructionARM::EmulateB,
13279 &EmulateInstructionARM::EmulateBLXImmediate, "bl <label>"},
13282 &EmulateInstructionARM::EmulateBLXImmediate, "blx <label>"},
13284 &EmulateInstructionARM::EmulateBLXRm, "blx <Rm>"},
13287 &EmulateInstructionARM::EmulateBXRm, "bx <Rm>"},
13290 &EmulateInstructionARM::EmulateBXJRm, "bxj <Rm>"},
13293 &EmulateInstructionARM::EmulateCB, "cb{n}z <Rn>, <label>"},
13296 &EmulateInstructionARM::EmulateTB, "tbb<c> <Rn>, <Rm>"},
13299 &EmulateInstructionARM::EmulateTB, "tbh<c> <Rn>, <Rm>, lsl #1"},
13304 &EmulateInstructionARM::EmulateADCImm, "adc{s}<c> <Rd>, <Rn>, #<const>"},
13307 &EmulateInstructionARM::EmulateADCReg, "adcs|adc<c> <Rdn>, <Rm>"},
13309 &EmulateInstructionARM::EmulateADCReg,
13313 &EmulateInstructionARM::EmulateADDReg, "adds|add<c> <Rd>, <Rn>, <Rm>"},
13317 &EmulateInstructionARM::EmulateADDReg, "add<c> <Rdn>, <Rm>"},
13320 &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
13322 &EmulateInstructionARM::EmulateADR, "sub<c> <Rd>, PC, #<const>"},
13324 &EmulateInstructionARM::EmulateADR, "add<c> <Rd>, PC, #<const>"},
13327 &EmulateInstructionARM::EmulateANDImm, "and{s}<c> <Rd>, <Rn>, #<const>"},
13330 &EmulateInstructionARM::EmulateANDReg, "ands|and<c> <Rdn>, <Rm>"},
13332 &EmulateInstructionARM::EmulateANDReg,
13336 &EmulateInstructionARM::EmulateBICImm, "bic{s}<c> <Rd>, <Rn>, #<const>"},
13339 &EmulateInstructionARM::EmulateBICReg, "bics|bic<c> <Rdn>, <Rm>"},
13341 &EmulateInstructionARM::EmulateBICReg,
13345 &EmulateInstructionARM::EmulateEORImm, "eor{s}<c> <Rd>, <Rn>, #<const>"},
13348 &EmulateInstructionARM::EmulateEORReg, "eors|eor<c> <Rdn>, <Rm>"},
13350 &EmulateInstructionARM::EmulateEORReg,
13354 &EmulateInstructionARM::EmulateORRImm, "orr{s}<c> <Rd>, <Rn>, #<const>"},
13357 &EmulateInstructionARM::EmulateORRReg, "orrs|orr<c> <Rdn>, <Rm>"},
13359 &EmulateInstructionARM::EmulateORRReg,
13363 &EmulateInstructionARM::EmulateRSBImm, "rsbs|rsb<c> <Rd>, <Rn>, #0"},
13365 &EmulateInstructionARM::EmulateRSBImm,
13369 &EmulateInstructionARM::EmulateRSBReg,
13373 &EmulateInstructionARM::EmulateSBCImm, "sbc{s}<c> <Rd>, <Rn>, #<const>"},
13376 &EmulateInstructionARM::EmulateSBCReg, "sbcs|sbc<c> <Rdn>, <Rm>"},
13378 &EmulateInstructionARM::EmulateSBCReg,
13382 &EmulateInstructionARM::EmulateADDImmThumb,
13385 &EmulateInstructionARM::EmulateADDImmThumb, "adds|add<c> <Rdn>,#<imm8>"},
13387 &EmulateInstructionARM::EmulateADDImmThumb,
13390 &EmulateInstructionARM::EmulateADDImmThumb,
13394 &EmulateInstructionARM::EmulateSUBImmThumb,
13397 &EmulateInstructionARM::EmulateSUBImmThumb, "subs|sub<c> <Rdn>, #imm8"},
13399 &EmulateInstructionARM::EmulateSUBImmThumb,
13402 &EmulateInstructionARM::EmulateSUBImmThumb,
13406 &EmulateInstructionARM::EmulateSUBSPImm, "sub{s}.w <Rd>, sp, #<const>"},
13408 &EmulateInstructionARM::EmulateSUBSPImm, "subw<c> <Rd>, sp, #imm12"},
13411 &EmulateInstructionARM::EmulateSUBReg, "subs|sub<c> <Rd>, <Rn>, <Rm>"},
13413 &EmulateInstructionARM::EmulateSUBReg,
13417 &EmulateInstructionARM::EmulateTEQImm, "teq<c> <Rn>, #<const>"},
13420 &EmulateInstructionARM::EmulateTEQReg, "teq<c> <Rn>, <Rm> {,<shift>}"},
13423 &EmulateInstructionARM::EmulateTSTImm, "tst<c> <Rn>, #<const>"},
13426 &EmulateInstructionARM::EmulateTSTReg, "tst<c> <Rdn>, <Rm>"},
13428 &EmulateInstructionARM::EmulateTSTReg, "tst<c>.w <Rn>, <Rm> {,<shift>}"},
13432 &EmulateInstructionARM::EmulateMOVRdRm, "mov<c> <Rd>, <Rm>"},
13435 &EmulateInstructionARM::EmulateMOVRdRm, "movs <Rd>, <Rm>"},
13438 &EmulateInstructionARM::EmulateMOVRdRm, "mov{s}<c>.w <Rd>, <Rm>"},
13441 &EmulateInstructionARM::EmulateMOVRdImm, "movs|mov<c> <Rd>, #imm8"},
13443 &EmulateInstructionARM::EmulateMOVRdImm, "mov{s}<c>.w <Rd>, #<const>"},
13445 &EmulateInstructionARM::EmulateMOVRdImm, "movw<c> <Rd>,#<imm16>"},
13448 &EmulateInstructionARM::EmulateMVNImm, "mvn{s} <Rd>, #<const>"},
13451 &EmulateInstructionARM::EmulateMVNReg, "mvns|mvn<c> <Rd>, <Rm>"},
13453 &EmulateInstructionARM::EmulateMVNReg,
13457 &EmulateInstructionARM::EmulateCMNImm, "cmn<c> <Rn>, #<const>"},
13460 &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm>"},
13462 &EmulateInstructionARM::EmulateCMNReg, "cmn<c> <Rn>, <Rm> {,<shift>}"},
13465 &EmulateInstructionARM::EmulateCMPImm, "cmp<c> <Rn>, #imm8"},
13467 &EmulateInstructionARM::EmulateCMPImm, "cmp<c>.w <Rn>, #<const>"},
13470 &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
13473 &EmulateInstructionARM::EmulateCMPReg, "cmp<c> <Rn>, <Rm>"},
13475 &EmulateInstructionARM::EmulateCMPReg,
13479 &EmulateInstructionARM::EmulateASRImm, "asrs|asr<c> <Rd>, <Rm>, #imm"},
13481 &EmulateInstructionARM::EmulateASRImm, "asr{s}<c>.w <Rd>, <Rm>, #imm"},
13484 &EmulateInstructionARM::EmulateASRReg, "asrs|asr<c> <Rdn>, <Rm>"},
13486 &EmulateInstructionARM::EmulateASRReg, "asr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13489 &EmulateInstructionARM::EmulateLSLImm, "lsls|lsl<c> <Rd>, <Rm>, #imm"},
13491 &EmulateInstructionARM::EmulateLSLImm, "lsl{s}<c>.w <Rd>, <Rm>, #imm"},
13494 &EmulateInstructionARM::EmulateLSLReg, "lsls|lsl<c> <Rdn>, <Rm>"},
13496 &EmulateInstructionARM::EmulateLSLReg, "lsl{s}<c>.w <Rd>, <Rn>, <Rm>"},
13499 &EmulateInstructionARM::EmulateLSRImm, "lsrs|lsr<c> <Rd>, <Rm>, #imm"},
13501 &EmulateInstructionARM::EmulateLSRImm, "lsr{s}<c>.w <Rd>, <Rm>, #imm"},
13504 &EmulateInstructionARM::EmulateLSRReg, "lsrs|lsr<c> <Rdn>, <Rm>"},
13506 &EmulateInstructionARM::EmulateLSRReg, "lsr{s}<c>.w <Rd>, <Rn>, <Rm>"},
13509 &EmulateInstructionARM::EmulateRRX, "rrx{s}<c>.w <Rd>, <Rm>"},
13512 &EmulateInstructionARM::EmulateRORImm, "ror{s}<c>.w <Rd>, <Rm>, #imm"},
13515 &EmulateInstructionARM::EmulateRORReg, "rors|ror<c> <Rdn>, <Rm>"},
13517 &EmulateInstructionARM::EmulateRORReg, "ror{s}<c>.w <Rd>, <Rn>, <Rm>"},
13520 &EmulateInstructionARM::EmulateMUL, "muls <Rdm>,<Rn>,<Rdm>"},
13523 &EmulateInstructionARM::EmulateMUL, "mul<c> <Rd>,<Rn>,<Rm>"},
13527 &EmulateInstructionARM::EmulateSUBSPcLrEtc, "SUBS<c> PC, LR, #<imm8>"},
13534 &EmulateInstructionARM::EmulateRFE, "rfedb<c> <Rn>{!}"},
13536 &EmulateInstructionARM::EmulateRFE, "rfe{ia}<c> <Rn>{!}"},
13540 &EmulateInstructionARM::EmulateLDM, "ldm<c> <Rn>{!} <registers>"},
13542 &EmulateInstructionARM::EmulateLDM, "ldm<c>.w <Rn>{!} <registers>"},
13544 &EmulateInstructionARM::EmulateLDMDB, "ldmdb<c> <Rn>{!} <registers>"},
13546 &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [<Rn>{,#imm}]"},
13548 &EmulateInstructionARM::EmulateLDRRtRnImm, "ldr<c> <Rt>, [SP{,#imm}]"},
13550 &EmulateInstructionARM::EmulateLDRRtRnImm,
13553 &EmulateInstructionARM::EmulateLDRRtRnImm,
13557 &EmulateInstructionARM::EmulateLDRRtPCRelative,
13560 &EmulateInstructionARM::EmulateLDRRegister, "ldr<c> <Rt>, [<Rn>, <Rm>]"},
13562 &EmulateInstructionARM::EmulateLDRRegister,
13565 &EmulateInstructionARM::EmulateLDRBImmediate,
13568 &EmulateInstructionARM::EmulateLDRBImmediate,
13571 &EmulateInstructionARM::EmulateLDRBImmediate,
13574 &EmulateInstructionARM::EmulateLDRBLiteral, "ldrb<c> <Rt>,[...]"},
13576 &EmulateInstructionARM::EmulateLDRBRegister, "ldrb<c> <Rt>,[<Rn>,<Rm>]"},
13578 &EmulateInstructionARM::EmulateLDRBRegister,
13581 &EmulateInstructionARM::EmulateLDRHImmediate,
13584 &EmulateInstructionARM::EmulateLDRHImmediate,
13587 &EmulateInstructionARM::EmulateLDRHImmediate,
13590 &EmulateInstructionARM::EmulateLDRHLiteral, "ldrh<c> <Rt>, <label>"},
13592 &EmulateInstructionARM::EmulateLDRHRegister,
13595 &EmulateInstructionARM::EmulateLDRHRegister,
13598 &EmulateInstructionARM::EmulateLDRSBImmediate,
13601 &EmulateInstructionARM::EmulateLDRSBImmediate,
13604 &EmulateInstructionARM::EmulateLDRSBLiteral, "ldrsb<c> <Rt>, <label>"},
13606 &EmulateInstructionARM::EmulateLDRSBRegister,
13609 &EmulateInstructionARM::EmulateLDRSBRegister,
13612 &EmulateInstructionARM::EmulateLDRSHImmediate,
13615 &EmulateInstructionARM::EmulateLDRSHImmediate,
13618 &EmulateInstructionARM::EmulateLDRSHLiteral, "ldrsh<c> <Rt>,<label>"},
13620 &EmulateInstructionARM::EmulateLDRSHRegister,
13623 &EmulateInstructionARM::EmulateLDRSHRegister,
13626 &EmulateInstructionARM::EmulateLDRDImmediate,
13629 &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
13631 &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
13633 &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
13635 &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, {<Rn>{,#+/-<imm>}]"},
13637 &EmulateInstructionARM::EmulateVLD1Multiple,
13640 &EmulateInstructionARM::EmulateVLD1Single,
13643 &EmulateInstructionARM::EmulateVLD1SingleAll,
13648 &EmulateInstructionARM::EmulateSTM, "stm<c> <Rn>{!} <registers>"},
13650 &EmulateInstructionARM::EmulateSTM, "stm<c>.w <Rn>{!} <registers>"},
13652 &EmulateInstructionARM::EmulateSTMDB, "stmdb<c> <Rn>{!} <registers>"},
13654 &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [<Rn>{,#<imm>}]"},
13656 &EmulateInstructionARM::EmulateSTRThumb, "str<c> <Rt>, [SP,#<imm>]"},
13658 &EmulateInstructionARM::EmulateSTRThumb,
13661 &EmulateInstructionARM::EmulateSTRThumb,
13664 &EmulateInstructionARM::EmulateSTRRegister, "str<c> <Rt> ,{<Rn>, <Rm>]"},
13666 &EmulateInstructionARM::EmulateSTRRegister,
13669 &EmulateInstructionARM::EmulateSTRBThumb,
13672 &EmulateInstructionARM::EmulateSTRBThumb,
13675 &EmulateInstructionARM::EmulateSTRBThumb,
13678 &EmulateInstructionARM::EmulateSTRHRegister, "strh<c> <Rt>,[<Rn>,<Rm>]"},
13680 &EmulateInstructionARM::EmulateSTRHRegister,
13683 &EmulateInstructionARM::EmulateSTREX,
13686 &EmulateInstructionARM::EmulateSTRDImm,
13689 &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
13691 &EmulateInstructionARM::EmulateVSTM, "vstm{mode}<c> <Rn>{!}, <list>"},
13693 &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
13695 &EmulateInstructionARM::EmulateVSTR, "vstr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
13697 &EmulateInstructionARM::EmulateVST1Multiple,
13700 &EmulateInstructionARM::EmulateVST1Single,
13705 &EmulateInstructionARM::EmulateSXTB, "sxtb<c> <Rd>,<Rm>"},
13707 &EmulateInstructionARM::EmulateSXTB, "sxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13709 &EmulateInstructionARM::EmulateSXTH, "sxth<c> <Rd>,<Rm>"},
13711 &EmulateInstructionARM::EmulateSXTH, "sxth<c>.w <Rd>,<Rm>{,<rotation>}"},
13713 &EmulateInstructionARM::EmulateUXTB, "uxtb<c> <Rd>,<Rm>"},
13715 &EmulateInstructionARM::EmulateUXTB, "uxtb<c>.w <Rd>,<Rm>{,<rotation>}"},
13717 &EmulateInstructionARM::EmulateUXTH, "uxth<c> <Rd>,<Rm>"},
13719 &EmulateInstructionARM::EmulateUXTH, "uxth<c>.w <Rd>,<Rm>{,<rotation>}"},
13731 bool EmulateInstructionARM::SetArchitecture(const ArchSpec &arch) {
13764 bool EmulateInstructionARM::SetInstruction(const Opcode &insn_opcode,
13791 bool EmulateInstructionARM::ReadInstruction() {
13842 uint32_t EmulateInstructionARM::ArchVersion() { return m_arm_isa; }
13844 bool EmulateInstructionARM::ConditionPassed(const uint32_t opcode) {
13917 uint32_t EmulateInstructionARM::CurrentCond(const uint32_t opcode) {
13948 bool EmulateInstructionARM::InITBlock() {
13952 bool EmulateInstructionARM::LastInITBlock() {
13956 bool EmulateInstructionARM::BadMode(uint32_t mode) {
13981 bool EmulateInstructionARM::CurrentModeIsPrivileged() {
13993 void EmulateInstructionARM::CPSRWriteByInstr(uint32_t value, uint32_t bytemask,
14029 bool EmulateInstructionARM::BranchWritePC(const Context &context,
14045 bool EmulateInstructionARM::BXWritePC(Context &context, uint32_t addr) {
14080 bool EmulateInstructionARM::LoadWritePC(Context &context, uint32_t addr) {
14089 bool EmulateInstructionARM::ALUWritePC(Context &context, uint32_t addr) {
14096 EmulateInstructionARM::Mode EmulateInstructionARM::CurrentInstrSet() {
14103 bool EmulateInstructionARM::SelectInstrSet(Mode arm_or_thumb) {
14123 bool EmulateInstructionARM::UnalignedSupport() {
14131 EmulateInstructionARM::AddWithCarryResult
14132 EmulateInstructionARM::AddWithCarry(uint32_t x, uint32_t y, uint8_t carry_in) {
14153 uint32_t EmulateInstructionARM::ReadCoreReg(uint32_t num, bool *success) {
14215 bool EmulateInstructionARM::WriteCoreRegOptionalFlags(
14255 bool EmulateInstructionARM::WriteFlags(Context &context, const uint32_t result,
14273 bool EmulateInstructionARM::EvaluateInstruction(uint32_t evaluate_options) {
14318 opcode_data->callback != &EmulateInstructionARM::EmulateIT))
14342 EmulateInstructionARM::GetInstructionCondition() {
14349 bool EmulateInstructionARM::TestEmulation(Stream &out_stream, ArchSpec &arch,
14436 // EmulateInstructionARM::GetRegisterName (uint32_t reg_kind, uint32_t reg_num)
14457 bool EmulateInstructionARM::CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) {
14467 unwind_plan.SetSourceName("EmulateInstructionARM");