Lines Matching +full:0 +full:xac000000
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
26 constexpr uint64_t ppc64TocOffset = 0x8000;
27 constexpr uint64_t dynamicThreadPointerOffset = 0x8000;
82 constexpr uint32_t NOP = 0x60000000;
85 NOINSN = 0,
87 LBZ = 0x88000000,
88 LHZ = 0xa0000000,
89 LWZ = 0x80000000,
90 LHA = 0xa8000000,
91 LWA = 0xe8000002,
92 LD = 0xe8000000,
93 LFS = 0xC0000000,
94 LXSSP = 0xe4000003,
95 LFD = 0xc8000000,
96 LXSD = 0xe4000002,
97 LXV = 0xf4000001,
98 LXVP = 0x18000000,
101 STB = 0x98000000,
102 STH = 0xb0000000,
103 STW = 0x90000000,
104 STD = 0xf8000000,
105 STFS = 0xd0000000,
106 STXSSP = 0xf4000003,
107 STFD = 0xd8000000,
108 STXSD = 0xf4000002,
109 STXV = 0xf4000005,
110 STXVP = 0x18000001
113 NOINSN = 0,
114 PREFIX_MLS = 0x0610000000000000,
115 PREFIX_8LS = 0x0410000000000000,
122 PLWA = PREFIX_8LS | 0xa4000000,
123 PLD = PREFIX_8LS | 0xe4000000,
125 PLXSSP = PREFIX_8LS | 0xac000000,
127 PLXSD = PREFIX_8LS | 0xa8000000,
128 PLXV = PREFIX_8LS | 0xc8000000,
129 PLXVP = PREFIX_8LS | 0xe8000000,
135 PSTD = PREFIX_8LS | 0xf4000000,
137 PSTXSSP = PREFIX_8LS | 0xbc000000,
139 PSTXSD = PREFIX_8LS | 0xb8000000,
140 PSTXV = PREFIX_8LS | 0xd8000000,
141 PSTXVP = PREFIX_8LS | 0xf8000000
162 NOMASK = 0x0,
163 OPC_AND_RST = 0xffe00000, // Primary opc (0-5) and R[ST] (6-10).
164 ONLY_RST = 0x3e00000, // [RS]T (6-10).
166 0x8000000003e00000, // S/T (6-10) - The [S/T]X bit moves from 28 to 5.
215 // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
225 // 0 --> Zero offset between the GEP and LEP, and the function does NOT use
236 return 0;
244 return 0;
259 /*size=*/0, /*section=*/nullptr});
265 // firstInsn+0x200008; ...; ${prefix}31: firstInsn+(31-14)*0x200008; $tail
278 write32(ptr++, firstInsn + 0x200008 * (r - from));
313 constexpr uint32_t blr = 0x4e800020, mtlr_0 = 0x7c0803a6;
316 // Tail: ld 0, 16(1); mtlr 0; blr
317 writeSequence(restgpr0, "_restgpr0_", 14, 0xe9c1ff70,
318 {0xe8010010, mtlr_0, blr});
321 writeSequence(restgpr1, "_restgpr1_", 14, 0xe9ccff70, {blr});
323 // Tail: std 0, 16(1); blr
324 writeSequence(savegpr0, "_savegpr0_", 14, 0xf9c1ff70, {0xf8010010, blr});
327 writeSequence(savegpr1, "_savegpr1_", 14, 0xf9ccff70, {blr});
335 // r_offset: 0, 8, 16, etc. For a given Offset, Offset / 8 gives us the
353 if (relas[index].r_offset < offset || index == 0)
366 // ld/lwa 3, 0(3) # load the value from the address
377 // ld/lwa 3, 0(3) # load the value from the address
383 if (rel.addend < 0)
423 static uint64_t ha(uint64_t v) { return (v + 0x8000) >> 16; }
425 static uint16_t highera(uint64_t v) { return (v + 0x8000) >> 32; }
427 static uint16_t highesta(uint64_t v) { return (v + 0x8000) >> 48; }
444 return (encoding & 3) == 0x1;
464 uint32_t opc = encoding & 0xfc000000;
468 if ((opc == 0xe4000000 || opc == 0xe8000000 || opc == 0xf4000000 ||
469 opc == 0xf8000000) &&
471 opc = encoding & 0xfc000003;
472 else if (opc == 0xf4000000)
473 opc = encoding & 0xfc000007;
474 else if (opc == 0x18000000)
475 opc = encoding & 0xfc00000f;
516 pcrelEncoding |= (encoding & 0x8) << 23;
548 // paddi 3, 0, 1000, 1
553 ((prefixedInsn & 0x3ffff00000000) >> 16) | (prefixedInsn & 0xffff), 34);
554 int32_t disp16 = llvm::SignExtend32(accessInsn & 0xffff, 16);
557 disp16 &= ~0xf;
559 disp16 &= ~0x3;
612 // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
613 // use 0x10000000 as the starting address.
614 defaultImageBase = 0x10000000;
616 write32(trapInstr.data(), 0x7fe00008);
664 writeFromHalf16(loc, (insn & 0x03ffffff) | 0x38000000);
672 if ((insn & 0xfc000000) != 0xe4000000)
674 insn &= ~0xff000000fc000000;
676 // Replace the cleared bits with the values for PADDI (0x600000038000000);
677 insn |= 0x600000038000000;
695 "unrecognized instruction for R_PPC64_PCREL_OPT relaxation: 0x" +
706 ((totalDisp & 0x3ffff0000) << 16) |
707 (totalDisp & 0xffff));
739 writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13
743 // Relax from paddi r3, 0, x@got@tlsgd@pcrel, 1 to
744 // paddi r3, r13, x@tprel, 0
745 writePrefixedInstruction(loc, 0x06000000386d0000);
759 if (locAsInt % 4 == 0) {
761 write32(loc + 4, 0x38630000); // addi r3, r3
765 relocateNoSym(loc + 4 + (config->ekind == ELF64BEKind ? 2 : 0),
792 // addi r3, r3, x@got@tlsld@l into addis r3, r13, 0
801 writeFromHalf16(loc, 0x3c6d0000); // addis r3, r13, 0
804 // Relax from paddi r3, 0, x1@got@tlsld@pcrel, 1 to
805 // paddi r3, r13, 0x1000, 0
806 writePrefixedInstruction(loc, 0x06000000386d1000);
820 if (locAsInt % 4 == 0) {
822 write32(loc + 4, 0x38631000); // addi r3, r3, 4096
850 return (LWA << 26) | 0x2;
856 return 0;
887 return 0;
912 unsigned offset = (config->ekind == ELF64BEKind) ? 2 : 0;
919 uint32_t regNo = read32(loc - offset) & 0x03E00000; // bits 6-10
920 write32(loc - offset, 0x3C0D0000 | regNo); // addis RegNo, r13
925 const uint64_t pldRT = readPrefixedInstruction(loc) & 0x0000000003e00000;
926 // paddi RT(from pld), r13, symbol@tprel, 0
927 writePrefixedInstruction(loc, 0x06000000380d0000 | pldRT);
933 if (locAsInt % 4 == 0) {
937 uint32_t secondaryOp = (read32(loc) & 0x000007FE) >> 1; // bits 21-30
940 if (dFormOp == 0) { // Expecting a DS-Form instruction.
942 if (dFormOp == 0)
947 write32(loc, dFormOp | (read32(loc) & 0x03ff0000));
957 uint32_t secondaryOp = (tlsInstr & 0x000007FE) >> 1; // bits 21-30
963 uint32_t rt = (tlsInstr & 0x03E00000) >> 21; // bits 6-10
964 uint32_t ra = (tlsInstr & 0x001F0000) >> 16; // bits 11-15
969 write32(loc - 1, 0x7C000378 | (rt << 16) | (ra << 21) | (ra << 11));
973 if (dFormOp == 0) { // Expecting a DS-Form instruction.
975 if (dFormOp == 0)
978 write32(loc - 1, (dFormOp | (tlsInstr & 0x03ff0000)));
1117 return 0;
1131 return 0;
1141 write32(buf + 0, 0x7c0802a6); // mflr r0
1142 write32(buf + 4, 0x429f0005); // bcl 20,4*cr7+so,8 <_glink+0x8>
1143 write32(buf + 8, 0x7d6802a6); // mflr r11
1144 write32(buf + 12, 0x7c0803a6); // mtlr r0
1145 write32(buf + 16, 0x7d8b6050); // subf r12, r11, r12
1146 write32(buf + 20, 0x380cffcc); // subi r0,r12,52
1147 write32(buf + 24, 0x7800f082); // srdi r0,r0,62,2
1148 write32(buf + 28, 0xe98b002c); // ld r12,44(r11)
1149 write32(buf + 32, 0x7d6c5a14); // add r11,r12,r11
1150 write32(buf + 36, 0xe98b0000); // ld r12,0(r11)
1151 write32(buf + 40, 0xe96b0008); // ld r11,8(r11)
1152 write32(buf + 44, 0x7d8903a6); // mtctr r12
1153 write32(buf + 48, 0x4e800420); // bctr
1166 write32(buf, 0x48000000 | ((-offset) & 0x03FFFFFc));
1271 write16(loc + 2, (aalk & 3) | (val & 0xfffc));
1287 uint16_t mask = isDQFormInstruction(readFromHalf16(loc)) ? 0xf : 0x3;
1294 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0)
1297 checkInt(loc, val + 0x8000, 32, rel);
1329 // When the high-adjusted part of a toc relocation evaluates to 0, it is
1332 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) {
1336 "can't toc-optimize an update instruction: 0x" +
1338 writeFromHalf16(loc, (insn & 0xffe00000) | 0x00020000 | lo(val));
1348 uint16_t mask = isDQFormInstruction(insn) ? 0xf : 0x3;
1350 if (config->tocOptimize && shouldTocOptimize && ha(val) == 0) {
1351 // When the high-adjusted part of a toc relocation evaluates to 0, it is
1356 "Can't toc-optimize an update instruction: 0x" +
1358 insn &= 0xffe00000 | mask;
1359 writeFromHalf16(loc, insn | 0x00020000 | lo(val));
1378 uint32_t mask = 0x0000FFFC;
1386 uint32_t mask = 0x03FFFFFC;
1396 // The Dynamic Thread Vector actually points 0x8000 bytes past the start
1407 const uint64_t si0Mask = 0x00000003ffff0000;
1408 const uint64_t si1Mask = 0x000000000000ffff;
1409 const uint64_t fullMask = 0x0003ffff0000ffff;
1462 // 0x2000000 = (1 << 24-1) * 4
1463 return 0x2000000;
1489 if ((readPrefixedInstruction(loc) & 0xfc000000) == 0xe4000000)
1524 uint32_t ra = (readFromHalf16(loc) & (0x1f << 16));
1525 writeFromHalf16(loc, 0xe8600000 | ra);
1530 // Relax from paddi r3, 0, sym@got@tlsgd@pcrel, 1 to
1532 writePrefixedInstruction(loc, 0x04100000e4600000);
1547 if (locAsInt % 4 == 0) {
1549 write32(loc + 4, 0x7c636A14); // nop --> add r3, r3, r13
1552 write32(loc - 1, 0x7c636a14);
1604 if (read32(loc) == 0x60000000) // nop
1607 // Patch a nop (0x60000000) to a ld.
1614 read32(loc + 4) != 0x60000000) &&
1622 write32(loc + 4, 0xe8410018); // ld %r2, 24(%r1)
1653 // ld r0,-0x7000-64(r13)
1687 // First instruction must be `ld r0, -0x7000-64(r13)`
1688 if (read32(loc) != 0xe80d8fc0)
1691 int16_t hiImm = 0;
1692 int16_t loImm = 0;
1697 hiImm = firstInstr & 0xFFFF;
1699 loImm = firstInstr & 0xFFFF;
1708 loImm = secondInstr & 0xFFFF;
1718 return ((instr & 0x3E00000) >> 21 == expectedRT) &&
1719 ((instr & 0x1F0000) >> 16 == expectedRA);
1737 loImm = adjustedStackFrameSize & 0xFFFF;
1738 hiImm = (adjustedStackFrameSize + 0x8000) >> 16;
1740 write32(loc + 4, 0x3D810000 | (uint16_t)hiImm);
1742 secondInstr = loImm ? 0x398C0000 | (uint16_t)loImm : NOP;
1746 write32(loc + 4, (0x39810000) | (uint16_t)loImm);