Lines Matching +full:hi +full:- +full:fi
1 //===- X86.cpp ------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
19 /// IsX86_MMXType - Return true if this is an MMX type.
22 return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 &&
23 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() &&
24 IRType->getScalarSizeInBits() != 64;
33 if (IsMMXCons && Ty->isVectorTy()) {
34 if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedValue() !=
45 return llvm::FixedVectorType::get(Int1Ty, Ty->getScalarSizeInBits());
55 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
56 if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) {
57 if (BT->getKind() == BuiltinType::LongDouble) {
64 } else if (const VectorType *VT = Ty->getAs<VectorType>()) {
88 //===----------------------------------------------------------------------===//
89 // X86-32 ABI Implementation
90 //===----------------------------------------------------------------------===//
94 CCState(CGFunctionInfo &FI)
95 : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()),
96 Required(FI.getRequiredArgs()), IsDelegateCall(FI.isDelegateCall()) {}
106 /// X86_32ABIInfo - The X86-32 ABI information.
140 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
166 void rewriteWithInAlloca(CGFunctionInfo &FI) const;
171 void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const;
175 void computeInfo(CGFunctionInfo &FI) const override;
198 // LLVM's x86-32 lowering currently only assigns up to three
275 OS << StringRef(&AsmString[Pos], DollarEnd - Pos);
277 size_t NumDollars = DollarEnd - DollarStart;
288 StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart);
336 /// shouldReturnTypeInRegister - Determine if the given type should be
343 // For the MCU ABI, it only needs to be <= 8-byte
347 if (Ty->isVectorType()) {
348 // 64- and 128- bit vectors inside structures are not returned in
358 if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() ||
359 Ty->isAnyComplexType() || Ty->isEnumeralType() ||
360 Ty->isBlockPointerType() || Ty->isMemberPointerType())
365 return shouldReturnTypeInRegister(AT->getElementType(), Context);
368 const RecordType *RT = Ty->getAs<RecordType>();
375 for (const auto *FD : RT->getDecl()->fields()) {
381 if (!shouldReturnTypeInRegister(FD->getType(), Context))
389 if (const ComplexType *CTy = Ty->getAs<ComplexType>())
390 Ty = CTy->getElementType();
392 // Check for a type which we know has a simple scalar argument-passing
394 // and 64-bit integer and integer-equivalents, float, and double.)
395 if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() &&
396 !Ty->isEnumeralType() && !Ty->isBlockPointerType())
405 for (const auto *FD : RD->fields()) {
407 // argument is smaller than 32-bits, expanding the struct will create
409 if (!is32Or64BitBasicType(FD->getType(), Context))
412 // FIXME: Reject bit-fields wholesale; there are two problems, we don't know
415 if (FD->isBitField())
418 Size += Context.getTypeSize(FD->getType());
425 // Don't do this if there are any non-empty bases.
426 for (const CXXBaseSpecifier &Base : RD->bases()) {
427 if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(),
442 const RecordType *RT = Ty->getAs<RecordType>();
445 const RecordDecl *RD = RT->getDecl();
449 // On non-Windows, we have to conservatively match our old bitcode
450 // prototypes in order to be ABI-compatible at the bitcode level.
451 if (!CXXRD->isCLike())
455 if (CXXRD->isDynamicClass())
474 --State.FreeRegs;
483 if (RetTy->isVoidType())
495 if (const VectorType *VT = RetTy->getAs<VectorType>()) {
500 // 128-bit vectors are a special case; they are returned in
510 (Size == 64 && VT->getNumElements() == 1))
521 if (const RecordType *RT = RetTy->getAs<RecordType>()) {
523 if (RT->getDecl()->hasFlexibleArrayMember())
528 if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType())
536 if (const ComplexType *CT = RetTy->getAs<ComplexType>()) {
537 QualType ET = getContext().getCanonicalType(CT->getElementType());
538 if (ET->isFloat16Type())
548 // As a special-case, if the struct is a "single-element" struct, and
550 // floating-point register. (MSVC does not apply this special case.)
554 if ((!IsWin32StructABI && SeltTy->isRealFloatingType())
555 || SeltTy->hasPointerRepresentation())
567 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
568 RetTy = EnumTy->getDecl()->getIntegerType();
570 if (const auto *EIT = RetTy->getAs<BitIntType>())
571 if (EIT->getNumBits() > 64)
590 if (Ty->isVectorType() && (Align == 16 || Align == 32 || Align == 64))
593 // On non-Darwin, the stack type alignment is always 4.
611 --State.FreeRegs; // Non-byval indirects just use one pointer.
636 if (const BuiltinType *BT = T->getAs<BuiltinType>()) {
637 BuiltinType::Kind K = BT->getKind();
663 // The MCU psABI allows passing parameters in-reg even if there are
665 // it does not allow passing >8-byte structs in-register,
671 State.FreeRegs -= SizeInRegs;
679 // they do not consume register slots. Homogenous floating-point aggregates
707 (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() ||
708 Ty->isReferenceType());
724 void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const {
727 // are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers.
734 MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
739 if ((Ty->isVectorType() || Ty->isBuiltinType()) &&
742 State.FreeSSERegs -= NumElts;
761 const RecordType *RT = Ty->getAs<RecordType>();
785 State.FreeSSERegs -= NumElts;
792 if (Ty->isBuiltinType() || Ty->isVectorType())
796 if (IsVectorCall && Ty->isBuiltinType())
804 if (RT && RT->getDecl()->hasFlexibleArrayMember())
807 // Ignore empty structs/unions on non-Windows.
826 // Pass over-aligned aggregates to non-variadic functions on Windows
835 getContext().getASTRecordLayout(RT->getDecl());
844 // Expand small (<= 128-bit) record types when we know that the stack layout
858 if (const VectorType *VT = Ty->getAs<VectorType>()) {
861 // user-defined vector types larger than 512 bits indirectly for simplicity.
864 --State.FreeSSERegs;
874 (TI.Width == 64 && VT->getNumElements() == 1))
886 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
887 Ty = EnumTy->getDecl()->getIntegerType();
897 if (const auto *EIT = Ty->getAs<BitIntType>()) {
898 if (EIT->getNumBits() <= 64) {
911 void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const {
912 CCState State(FI);
921 } else if (FI.getHasRegParm())
922 State.FreeRegs = FI.getRegParm();
934 if (!::classifyReturnType(getCXXABI(), FI, *this)) {
935 FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State);
936 } else if (FI.getReturnInfo().isIndirect()) {
940 --State.FreeRegs; // The sret parameter consumes a register.
942 FI.getReturnInfo().setInReg(true);
947 if (FI.isChainCall())
953 runVectorCallFirstPass(FI, State);
956 MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments();
970 rewriteWithInAlloca(FI);
977 // Arguments are always 4-byte-aligned.
998 CharUnits NumBytes = StackOffset - FieldEnd;
1026 void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const {
1036 CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end();
1040 FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall;
1041 ABIArgInfo &Ret = FI.getReturnInfo();
1043 isArgInAlloca(I->info)) {
1044 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1050 addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType());
1061 if (isArgInAlloca(I->info))
1062 addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type);
1065 FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields,
1081 // x86-32 changes the alignment of certain arguments on the stack.
1100 case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return
1102 case CodeGenOptions::SRCK_InRegs: // -freg-struct-return
1122 if (!FD->hasAttr<AnyX86InterruptAttr>())
1126 Fn->setCallingConv(llvm::CallingConv::X86_INTR);
1127 if (FD->getNumParams() == 0)
1130 auto PtrTy = cast<PointerType>(FD->getParamDecl(0)->getType());
1131 llvm::Type *ByValTy = CGM.getTypes().ConvertType(PtrTy->getPointeeType());
1133 Fn->getContext(), ByValTy);
1134 Fn->addParamAttr(0, NewAttr);
1139 if (GV->isDeclaration())
1142 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1144 Fn->addFnAttr("stackrealign");
1158 // 0-7 are the eight integer registers; the order is different
1164 // 12-16 are st(0..4). Not sure why we stop at 4.
1166 // platforms with 8-byte alignment for that type.
1177 // 11-16 are st(0..5). Not sure why we stop at 5.
1179 // platforms with 4-byte alignment for that type.
1187 //===----------------------------------------------------------------------===//
1188 // X86-64 ABI Implementation
1189 //===----------------------------------------------------------------------===//
1207 /// X86_64ABIInfo - The X86_64 ABI information.
1220 /// merge - Implement the X86_64 ABI merging algorithm.
1225 /// \param Accum - The accumulating classification. This should
1231 /// postMerge - Implement the X86_64 ABI post merging algorithm.
1233 /// Post merger cleanup, reduces a malformed Hi and Lo pair to
1236 /// \param AggregateSize - The size of the current aggregate in
1239 /// \param Lo - The classification for the parts of the type
1242 /// \param Hi - The classification for the parts of the type
1245 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1247 /// classify - Determine the x86_64 register classes in which the
1250 /// \param Lo - The classification for the parts of the type
1253 /// \param Hi - The classification for the parts of the type
1256 /// \param OffsetBase - The bit offset of this type in the
1260 /// \param isNamedArg - Whether the argument in question is a "named"
1261 /// argument, as used in AMD64-ABI 3.5.7.
1263 /// \param IsRegCall - Whether the calling conversion is regcall.
1271 /// If the \arg Lo class is ComplexX87, then the \arg Hi class will
1273 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1284 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1288 /// getIndirectResult - Give a source type \arg Ty, return a suitable result
1291 /// \param freeIntRegs - The number of free integer registers remaining
1348 // 64-bit hardware.
1364 return vectorTy->getPrimitiveSizeInBits().getFixedValue() > 128;
1369 void computeInfo(CGFunctionInfo &FI) const override;
1381 /// WinX86_64ABIInfo - The Windows X86_64 ABI information.
1388 void computeInfo(CGFunctionInfo &FI) const override;
1423 /// Disable tail call on x86-64. The epilogue code before the tail jump blocks
1435 // 0-15 are the 16 integer registers.
1449 // The default CC on x86-64 sets %al to the number of SSA
1455 if (fnType->getCallConv() == CC_C) {
1459 if (getABIInfo<X86_64ABIInfo>().isPassedUsingAVXType(it->Ty)) {
1474 if (GV->isDeclaration())
1477 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1479 Fn->addFnAttr("stackrealign");
1537 // Forbid 512-bit or larger vector pass or return when we disabled ZMM
1586 // change its ABI with attribute-target after this call.
1587 if (Arg.getType()->isVectorType() &&
1593 if (ArgIndex < Callee->getNumParams())
1594 Ty = Callee->getParamDecl(ArgIndex)->getType();
1604 // whether this value is used, tail-called, etc.
1605 if (Callee->getReturnType()->isVectorType() &&
1606 CGM.getContext().getTypeSize(Callee->getReturnType()) > 128) {
1609 CalleeMap, Callee->getReturnType(),
1656 if (GV->isDeclaration())
1682 // 0-15 are the 16 integer registers.
1705 if (GV->isDeclaration())
1708 if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) {
1710 Fn->addFnAttr("stackrealign");
1720 Class &Hi) const {
1721 // AMD64-ABI 3.2.3p2: Rule 5. Then a post merger cleanup is done:
1742 if (Hi == Memory)
1744 if (Hi == X87Up && Lo != X87 && honorsRevision0_98())
1746 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
1748 if (Hi == SSEUp && Lo != SSE)
1749 Hi = SSE;
1753 // AMD64-ABI 3.2.3p2: Rule 4. Each field of an object is
1793 Class &Hi, bool isNamedArg, bool IsRegCall) const {
1802 Lo = Hi = NoClass;
1804 Class &Current = OffsetBase < 64 ? Lo : Hi;
1807 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
1808 BuiltinType::Kind k = BT->getKind();
1814 Hi = Integer;
1822 Hi = SSEUp;
1827 Hi = SSEUp;
1830 Hi = X87Up;
1841 if (const EnumType *ET = Ty->getAs<EnumType>()) {
1843 classify(ET->getDecl()->getIntegerType(), OffsetBase, Lo, Hi, isNamedArg);
1847 if (Ty->hasPointerRepresentation()) {
1852 if (Ty->isMemberPointerType()) {
1853 if (Ty->isMemberFunctionPointerType()) {
1856 // Lo and Hi now.
1857 Lo = Hi = Integer;
1859 // Otherwise, with 32-bit pointers, this is an {i32, i32}. If that
1860 // straddles an eightbyte boundary, Hi should be classified as well.
1862 uint64_t EB_ThisAdj = (OffsetBase + 64 - 1) / 64;
1864 Lo = Hi = Integer;
1875 if (const VectorType *VT = Ty->getAs<VectorType>()) {
1879 // 4 bytes - <4 x char>, <2 x short>, <1 x int>, <1 x float>
1880 // 2 bytes - <2 x char>, <1 x short>
1881 // 1 byte - <1 x char>
1887 uint64_t EB_Hi = (OffsetBase + Size - 1) / 64;
1889 Hi = Lo;
1891 QualType ElementType = VT->getElementType();
1894 if (ElementType->isSpecificBuiltinType(BuiltinType::Double))
1901 (ElementType->isSpecificBuiltinType(BuiltinType::LongLong) ||
1902 ElementType->isSpecificBuiltinType(BuiltinType::ULongLong) ||
1903 ElementType->isSpecificBuiltinType(BuiltinType::Long) ||
1904 ElementType->isSpecificBuiltinType(BuiltinType::ULong)))
1912 Hi = Lo;
1915 QualType ElementType = VT->getElementType();
1919 (ElementType->isSpecificBuiltinType(BuiltinType::Int128) ||
1920 ElementType->isSpecificBuiltinType(BuiltinType::UInt128)))
1923 // Arguments of 256-bits are split into four eightbyte chunks. The
1925 // SSEUP. The original Lo and Hi design considers that types can't be
1926 // greater than 128-bits, so a 64-bit split in Hi and Lo makes sense.
1927 // This design isn't correct for 256-bits, but since there're no cases
1929 // complexity and just consider Hi to match the 64-256 part.
1931 // Note that per 3.5.7 of AMD64-ABI, 256-bit args are only passed in
1935 // Similarly, per 3.2.3. of the AVX512 draft, 512-bits ("named") args are
1938 Hi = SSEUp;
1943 if (const ComplexType *CT = Ty->getAs<ComplexType>()) {
1944 QualType ET = getContext().getCanonicalType(CT->getElementType());
1947 if (ET->isIntegralOrEnumerationType()) {
1951 Lo = Hi = Integer;
1952 } else if (ET->isFloat16Type() || ET == getContext().FloatTy ||
1953 ET->isBFloat16Type()) {
1956 Lo = Hi = SSE;
1964 Lo = Hi = SSE;
1973 if (Hi == NoClass && EB_Real != EB_Imag)
1974 Hi = Lo;
1979 if (const auto *EITy = Ty->getAs<BitIntType>()) {
1980 if (EITy->getNumBits() <= 64)
1982 else if (EITy->getNumBits() <= 128)
1983 Lo = Hi = Integer;
1993 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2000 // AMD64-ABI 3.2.3p2: Rule 1. If ..., or it contains unaligned
2004 if (OffsetBase % getContext().getTypeAlign(AT->getElementType()))
2010 uint64_t EltSize = getContext().getTypeSize(AT->getElementType());
2011 uint64_t ArraySize = AT->getZExtSize();
2013 // The only case a 256-bit wide vector could be used is when the array
2014 // contains a single 256-bit element. Since Lo and Hi logic isn't extended
2023 classify(AT->getElementType(), Offset, FieldLo, FieldHi, isNamedArg);
2025 Hi = merge(Hi, FieldHi);
2026 if (Lo == Memory || Hi == Memory)
2030 postMerge(Size, Lo, Hi);
2031 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2035 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2038 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger
2043 // AMD64-ABI 3.2.3p2: Rule 2. If a C++ object has either a non-trivial
2044 // copy constructor or a non-trivial destructor, it is passed by invisible
2049 const RecordDecl *RD = RT->getDecl();
2052 if (RD->hasFlexibleArrayMember())
2062 for (const auto &I : CXXRD->bases()) {
2063 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2066 cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
2070 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate exceeds a
2078 Hi = merge(Hi, FieldHi);
2079 if (Lo == Memory || Hi == Memory) {
2080 postMerge(Size, Lo, Hi);
2091 bool IsUnion = RT->isUnionType() && !UseClang11Compat;
2093 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2096 bool BitField = i->isBitField();
2098 // Ignore padding bit-fields.
2099 if (BitField && i->isUnnamedBitField())
2102 // AMD64-ABI 3.2.3p2: Rule 1. If the size of an object is larger than
2105 // The only case a 256-bit or a 512-bit wide vector could be used is when
2106 // the struct contains a single 256-bit or 512-bit element. Early check
2109 // FIXME: Extended the Lo and Hi logic properly to work for size wider
2112 ((!IsUnion && Size != getContext().getTypeSize(i->getType())) ||
2115 postMerge(Size, Lo, Hi);
2120 Offset % getContext().getTypeAlign(i->getType().getCanonicalType());
2121 // Note, skip this test for bit-fields, see below.
2124 postMerge(Size, Lo, Hi);
2130 // AMD64-ABI 3.2.3p2: Rule 3. If the size of the aggregate
2136 // Bit-fields require special handling, they do not force the
2140 assert(!i->isUnnamedBitField());
2142 uint64_t Size = i->getBitWidthValue(getContext());
2145 uint64_t EB_Hi = (Offset + Size - 1) / 64;
2156 classify(i->getType(), Offset, FieldLo, FieldHi, isNamedArg);
2158 Hi = merge(Hi, FieldHi);
2159 if (Lo == Memory || Hi == Memory)
2163 postMerge(Size, Lo, Hi);
2172 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2173 Ty = EnumTy->getDecl()->getIntegerType();
2175 if (Ty->isBitIntType())
2186 if (const VectorType *VecTy = Ty->getAs<VectorType>()) {
2191 QualType EltTy = VecTy->getElementType();
2193 (EltTy->isSpecificBuiltinType(BuiltinType::Int128) ||
2194 EltTy->isSpecificBuiltinType(BuiltinType::UInt128)))
2212 !Ty->isBitIntType()) {
2214 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2215 Ty = EnumTy->getDecl()->getIntegerType();
2225 // cases so that the mid-level optimizer knows the alignment of the byval.
2275 cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy(128)) {
2285 if (IRType->getTypeID() == llvm::Type::FP128TyID)
2298 /// BitsContainNoUserData - Return true if the specified [start,end) bit range
2315 unsigned EltSize = (unsigned)Context.getTypeSize(AT->getElementType());
2316 unsigned NumElts = (unsigned)AT->getZExtSize();
2324 unsigned EltStart = EltOffset < StartBit ? StartBit-EltOffset :0;
2325 if (!BitsContainNoUserData(AT->getElementType(), EltStart,
2326 EndBit-EltOffset, Context))
2333 if (const RecordType *RT = Ty->getAs<RecordType>()) {
2334 const RecordDecl *RD = RT->getDecl();
2339 for (const auto &I : CXXRD->bases()) {
2340 assert(!I.isVirtual() && !I.getType()->isDependentType() &&
2343 cast<CXXRecordDecl>(I.getType()->castAs<RecordType>()->getDecl());
2349 unsigned BaseStart = BaseOffset < StartBit ? StartBit-BaseOffset :0;
2351 EndBit-BaseOffset, Context))
2361 for (RecordDecl::field_iterator i = RD->field_begin(), e = RD->field_end();
2368 unsigned FieldStart = FieldOffset < StartBit ? StartBit-FieldOffset :0;
2369 if (!BitsContainNoUserData(i->getType(), FieldStart, EndBit-FieldOffset,
2382 /// getFPTypeAtOffset - Return a floating point type at the specified offset.
2385 if (IROffset == 0 && IRType->isFloatingPointTy())
2390 if (!STy->getNumContainedTypes())
2394 unsigned Elt = SL->getElementContainingOffset(IROffset);
2395 IROffset -= SL->getElementOffset(Elt);
2396 return getFPTypeAtOffset(STy->getElementType(Elt), IROffset, TD);
2401 llvm::Type *EltTy = ATy->getElementType();
2403 IROffset -= IROffset / EltSize * EltSize;
2410 /// GetSSETypeAtOffset - Return a type that will be passed by the backend in the
2417 (unsigned)getContext().getTypeSize(SourceTy) / 8 - SourceOffset;
2419 if (!T0 || T0->isDoubleTy())
2430 if (T0->is16bitFPTy() && SourceSize > 4)
2433 // avx512fp16-abi.c:pr51813_2 shows it works to return float for
2439 if (T0->isFloatTy() && T1->isFloatTy())
2442 if (T0->is16bitFPTy() && T1->is16bitFPTy()) {
2451 if (T0->is16bitFPTy() || T1->is16bitFPTy())
2458 /// GetINTEGERTypeAtOffset - The ABI specifies that a value should be passed in
2459 /// an 8-byte GPR. This means that we either have a scalar or we are talking
2460 /// about the high or low part of an up-to-16-byte struct. This routine picks
2467 /// the 8-byte value references. PrefType may be null.
2469 /// SourceTy is the source-level type for the entire argument. SourceOffset is
2475 // If we're dealing with an un-offset LLVM IR type, then it means that we're
2476 // returning an 8-byte unit starting with it. See if we can safely use it.
2478 // Pointers and int64's always fill the 8-byte unit.
2480 IRType->isIntegerTy(64))
2483 // If we have a 1/2/4-byte integer, we can use it only if the rest of the
2489 if (IRType->isIntegerTy(8) || IRType->isIntegerTy(16) ||
2490 IRType->isIntegerTy(32) ||
2493 cast<llvm::IntegerType>(IRType)->getBitWidth();
2504 if (IROffset < SL->getSizeInBytes()) {
2505 unsigned FieldIdx = SL->getElementContainingOffset(IROffset);
2506 IROffset -= SL->getElementOffset(FieldIdx);
2508 return GetINTEGERTypeAtOffset(STy->getElementType(FieldIdx), IROffset,
2514 llvm::Type *EltTy = ATy->getElementType();
2517 return GetINTEGERTypeAtOffset(EltTy, IROffset-EltOffset, SourceTy,
2531 std::min(TySizeInBytes-SourceOffset, 8U)*8);
2535 /// GetX86_64ByValArgumentPair - Given a high and low type that can ideally
2538 /// a by-value argument should be passed as i32* and the high part as float,
2541 GetX86_64ByValArgumentPair(llvm::Type *Lo, llvm::Type *Hi,
2544 // at offset 8. If the high and low parts we inferred are both 4-byte types
2548 llvm::Align HiAlign = TD.getABITypeAlign(Hi);
2550 assert(HiStart != 0 && HiStart <= 8 && "Invalid x86-64 argument pair!");
2559 // i8/i16/i32. This can also include pointers when they are 32-bit (X32 and
2562 if (Lo->isHalfTy() || Lo->isFloatTy())
2563 Lo = llvm::Type::getDoubleTy(Lo->getContext());
2565 assert((Lo->isIntegerTy() || Lo->isPointerTy())
2567 Lo = llvm::Type::getInt64Ty(Lo->getContext());
2571 llvm::StructType *Result = llvm::StructType::get(Lo, Hi);
2573 // Verify that the second element is at an 8-byte offset.
2574 assert(TD.getStructLayout(Result)->getElementOffset(1) == 8 &&
2575 "Invalid x86-64 argument pair!");
2581 // AMD64-ABI 3.2.3p4: Rule 1. Classify the return type with the
2583 X86_64ABIInfo::Class Lo, Hi;
2584 classify(RetTy, 0, Lo, Hi, /*isNamedArg*/ true);
2587 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2588 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2593 if (Hi == NoClass)
2597 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2605 // AMD64-ABI 3.2.3p4: Rule 2. Types of class memory are returned via
2610 // AMD64-ABI 3.2.3p4: Rule 3. If the class is INTEGER, the next
2617 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2619 if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
2620 RetTy = EnumTy->getDecl()->getIntegerType();
2622 if (RetTy->isIntegralOrEnumerationType() &&
2628 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
2634 // AMD64-ABI 3.2.3p4: Rule 6. If the class is X87, the value is
2635 // returned on the X87 stack in %st0 as 80-bit x87 number.
2640 // AMD64-ABI 3.2.3p4: Rule 8. If the class is COMPLEX_X87, the real
2644 assert(Hi == ComplexX87 && "Unexpected ComplexX87 classification.");
2651 switch (Hi) {
2653 // never occur as a hi class.
2656 llvm_unreachable("Invalid classification for hi word.");
2673 // AMD64-ABI 3.2.3p4: Rule 5. If the class is SSEUP, the eightbyte
2683 // AMD64-ABI 3.2.3p4: Rule 7. If the class is X87UP, the value is
2713 X86_64ABIInfo::Class Lo, Hi;
2714 classify(Ty, 0, Lo, Hi, isNamedArg, IsRegCall);
2718 assert((Hi != Memory || Lo == Memory) && "Invalid memory classification.");
2719 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2726 if (Hi == NoClass)
2730 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2734 // AMD64-ABI 3.2.3p3: Rule 1. If the class is MEMORY, pass the argument
2738 // AMD64-ABI 3.2.3p3: Rule 5. If the class is X87, X87UP or
2750 // AMD64-ABI 3.2.3p3: Rule 2. If the class is INTEGER, the next
2756 // Pick an 8-byte type based on the preferred type.
2761 if (Hi == NoClass && isa<llvm::IntegerType>(ResType)) {
2763 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
2764 Ty = EnumTy->getDecl()->getIntegerType();
2766 if (Ty->isIntegralOrEnumerationType() &&
2773 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
2785 switch (Hi) {
2787 // never occur as hi classes, and X87Up must be preceded by X87,
2792 llvm_unreachable("Invalid classification for hi word.");
2798 // Pick an 8-byte type based on the preferred type.
2816 // AMD64-ABI 3.2.3p3: Rule 4. If the class is SSEUP, the
2818 // register. This only happens when 128-bit vectors are passed.
2838 auto RT = Ty->getAs<RecordType>();
2841 if (RT->getDecl()->hasFlexibleArrayMember())
2845 if (auto CXXRD = dyn_cast<CXXRecordDecl>(RT->getDecl())) {
2846 if (CXXRD->isDynamicClass()) {
2851 for (const auto &I : CXXRD->bases())
2861 for (const auto *FD : RT->getDecl()->fields()) {
2862 QualType MTy = FD->getType();
2863 if (MTy->isRecordType() && !MTy->isUnionType()) {
2879 MTy = AT->getElementType();
2880 if (const auto *VT = MTy->getAs<VectorType>())
2904 void X86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
2906 const unsigned CallingConv = FI.getCallingConvention();
2912 Win64ABIInfo.computeInfo(FI);
2923 if (!::classifyReturnType(getCXXABI(), FI, *this)) {
2924 if (IsRegCall && FI.getReturnType()->getTypePtr()->isRecordType() &&
2925 !FI.getReturnType()->getTypePtr()->isUnionType()) {
2926 FI.getReturnInfo() = classifyRegCallStructType(
2927 FI.getReturnType(), NeededInt, NeededSSE, MaxVectorWidth);
2929 FreeIntRegs -= NeededInt;
2930 FreeSSERegs -= NeededSSE;
2932 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
2934 } else if (IsRegCall && FI.getReturnType()->getAs<ComplexType>() &&
2935 getContext().getCanonicalType(FI.getReturnType()
2936 ->getAs<ComplexType>()
2937 ->getElementType()) ==
2941 FI.getReturnInfo() = getIndirectReturnResult(FI.getReturnType());
2943 FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
2948 if (FI.getReturnInfo().isIndirect())
2949 --FreeIntRegs;
2951 FI.setMaxVectorWidth(MaxVectorWidth);
2954 if (FI.isChainCall())
2957 unsigned NumRequiredArgs = FI.getNumRequiredArgs();
2958 // AMD64-ABI 3.2.3p3: Once arguments are classified, the registers
2959 // get assigned (in left-to-right order) for passing as follows...
2961 for (CGFunctionInfo::arg_iterator it = FI.arg_begin(), ie = FI.arg_end();
2965 if (IsRegCall && it->type->isStructureOrClassType())
2966 it->info = classifyRegCallStructType(it->type, NeededInt, NeededSSE,
2969 it->info = classifyArgumentType(it->type, FreeIntRegs, NeededInt,
2972 // AMD64-ABI 3.2.3p3: If there are no registers available for any
2977 FreeIntRegs -= NeededInt;
2978 FreeSSERegs -= NeededSSE;
2979 if (MaxVectorWidth > FI.getMaxVectorWidth())
2980 FI.setMaxVectorWidth(MaxVectorWidth);
2982 it->info = getIndirectResult(it->type, FreeIntRegs);
2994 // AMD64-ABI 3.5.7p5: Step 7. Align l->overflow_arg_area upwards to a 16
3004 // AMD64-ABI 3.5.7p5: Step 8. Fetch type from l->overflow_arg_area.
3008 // AMD64-ABI 3.5.7p5: Step 9. Set l->overflow_arg_area to:
3009 // l->overflow_arg_area + sizeof(type).
3010 // AMD64-ABI 3.5.7p5: Step 10. Align l->overflow_arg_area upwards to
3020 // AMD64-ABI 3.5.7p5: Step 11. Return the fetched type.
3043 // AMD64-ABI 3.5.7p5: Step 1. Determine whether type may be passed
3050 // AMD64-ABI 3.5.7p5: Step 2. Compute num_gp to hold the number of
3054 // AMD64-ABI 3.5.7p5: Step 3. Verify whether arguments fit into
3055 // registers. In the case: l->gp_offset > 48 - num_gp * 8 or
3056 // l->fp_offset > 304 - num_fp * 16 go to step 7.
3067 InRegs = llvm::ConstantInt::get(CGF.Int32Ty, 48 - neededInt * 8);
3075 llvm::ConstantInt::get(CGF.Int32Ty, 176 - neededSSE * 16);
3089 // AMD64-ABI 3.5.7p5: Step 4. Fetch type from l->reg_save_area with
3090 // an offset of l->gp_offset and/or l->fp_offset. This may require
3110 assert(ST->getNumElements() == 2 && "Unexpected ABI info for mixed regs");
3111 llvm::Type *TyLo = ST->getElementType(0);
3112 llvm::Type *TyHi = ST->getElementType(1);
3113 assert((TyLo->isFPOrFPVectorTy() ^ TyHi->isFPOrFPVectorTy()) &&
3119 llvm::Value *RegLoAddr = TyLo->isFPOrFPVectorTy() ? FPAddr : GPAddr;
3120 llvm::Value *RegHiAddr = TyLo->isFPOrFPVectorTy() ? GPAddr : FPAddr;
3161 // to assume that the slots are 16-byte aligned, since the stack is
3162 // naturally 16-byte aligned and the prologue is expected to store
3177 RegAddrLo.withElementType(ST->getStructElementType(0)));
3180 RegAddrHi.withElementType(ST->getStructElementType(1)));
3186 // AMD64-ABI 3.5.7p5: Step 5. Set:
3187 // l->gp_offset = l->gp_offset + num_gp * 8
3188 // l->fp_offset = l->fp_offset + num_fp * 16.
3232 if (!Ty->isBuiltinType() && !Ty->isVectorType() &&
3234 FreeSSERegs -= NumElts;
3244 if (Ty->isVoidType())
3247 if (const EnumType *EnumTy = Ty->getAs<EnumType>())
3248 Ty = EnumTy->getDecl()->getIntegerType();
3254 const RecordType *RT = Ty->getAs<RecordType>();
3261 if (RT->getDecl()->hasFlexibleArrayMember())
3274 FreeSSERegs -= NumElts;
3275 if (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())
3282 (IsReturnType || Ty->isBuiltinType() || Ty->isVectorType())) {
3283 FreeSSERegs -= NumElts;
3287 } else if (!Ty->isBuiltinType() && !Ty->isVectorType()) {
3294 if (Ty->isMemberPointerType()) {
3298 if (LLTy->isPointerTy() || LLTy->isIntegerTy())
3302 if (RT || Ty->isAnyComplexType() || Ty->isMemberPointerType()) {
3312 if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) {
3313 switch (BT->getKind()) {
3347 if (Ty->isBitIntType()) {
3350 // However, non-power-of-two bit-precise integers will be passed as 1, 2, 4,
3361 void WinX86_64ABIInfo::computeInfo(CGFunctionInfo &FI) const {
3362 const unsigned CC = FI.getCallingConvention();
3370 SysVABIInfo.computeInfo(FI);
3383 if (!getCXXABI().classifyReturnType(FI))
3384 FI.getReturnInfo() = classify(FI.getReturnType(), FreeSSERegs, true,
3397 for (auto &I : FI.arguments()) {
3411 for (auto &I : FI.arguments())