Lines Matching defs:SSE
52 /// Returns true if this type can be passed in SSE registers with the
74 /// Returns true if this aggregate is small enough to be passed in SSE registers
599 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
927 // Since MSVC 2015, the first three SSE vectors have been passed in
1211 SSE,
1234 /// final MEMORY or SSE classes when necessary.
1321 /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
1730 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
1734 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
1746 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
1748 if (Hi == SSEUp && Lo != SSE)
1749 Hi = SSE;
1772 // (f) Otherwise class SSE is used.
1789 return SSE;
1819 Current = SSE;
1821 Lo = SSE;
1826 Lo = SSE;
1832 Current = SSE;
1836 // FIXME: _Decimal32 and _Decimal64 are SSE.
1837 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
1897 // gcc passes <1 x long long> as SSE but clang used to unconditionally
1907 Current = SSE;
1924 // least significant one belongs to class SSE and all the others to class
1936 // split into eight eightbyte chunks, one SSE and seven SSEUP.
1937 Lo = SSE;
1954 Current = SSE;
1956 Lo = Hi = SSE;
1964 Lo = Hi = SSE;
2031 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2411 /// low 8 bytes of an XMM register, corresponding to the SSE class.
2588 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2597 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2628 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
2629 // available SSE register of the sequence %xmm0, %xmm1 is used.
2630 case SSE:
2667 case SSE:
2677 // SSEUP should always be preceded by SSE, just widen.
2679 assert(Lo == SSE && "Unexpected SSEUp classification.");
2689 // extra bits in an SSE reg.
2719 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2730 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2773 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
2774 // available SSE register is used, the registers are taken in the
2776 case SSE: {
2808 case SSE:
2817 // eightbyte is passed in the upper half of the last used SSE
2820 assert(Lo == SSE && "Unexpected SSEUp classification");
3158 // SSE registers are spaced 16 bytes apart in the register save
3163 // all the SSE registers to the RSA.
3376 // We can use up to 4 SSE return registers with vectorcall.
3379 // RegCall gives us 16 SSE registers.
3388 // We can use up to 6 SSE register parameters with vectorcall.
3391 // RegCall gives us 16 SSE registers, we can reuse the return registers.