Lines Matching +full:use +full:- +full:case
1 //===--- PPC.h - Declare PPC target feature support -------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
119 .Case("440", ArchDefineName)
120 .Case("450", ArchDefineName | ArchDefine440)
121 .Case("601", ArchDefineName)
122 .Case("602", ArchDefineName | ArchDefinePpcgr)
123 .Case("603", ArchDefineName | ArchDefinePpcgr)
124 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
125 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
126 .Case("604", ArchDefineName | ArchDefinePpcgr)
127 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
128 .Case("620", ArchDefineName | ArchDefinePpcgr)
129 .Case("630", ArchDefineName | ArchDefinePpcgr)
130 .Case("7400", ArchDefineName | ArchDefinePpcgr)
131 .Case("7450", ArchDefineName | ArchDefinePpcgr)
132 .Case("750", ArchDefineName | ArchDefinePpcgr)
133 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr |
135 .Case("a2", ArchDefineA2)
175 .Case("future",
225 case 'O': // Zero
227 case 'f': // Floating point register
228 // Don't use floating point registers on soft float ABI.
232 case 'b': // Base register
238 case 'd': // Floating point register (containing 64-bit value)
239 case 'v': // Altivec vector register
240 // Don't use floating point and altivec vector registers
246 case 'w':
248 case 'd': // VSX vector register to hold vector double data
249 case 'f': // VSX vector register to hold vector float data
250 case 's': // VSX vector register to hold scalar double data
251 case 'w': // VSX vector register to hold scalar double data
252 case 'a': // Any VSX register
253 case 'c': // An individual CR bit
254 case 'i': // FP or VSX register to hold 64-bit integers data
262 case 'h': // `MQ', `CTR', or `LINK' register
263 case 'q': // `MQ' register
264 case 'c': // `CTR' register
265 case 'l': // `LINK' register
266 case 'x': // `CR' register (condition register) number 0
267 case 'y': // `CR' register (condition register)
268 case 'z': // `XER[CA]' carry bit (part of the XER register)
271 case 'I': // Signed 16-bit constant
272 case 'J': // Unsigned 16-bit constant shifted left 16 bits
273 // (use `L' instead for SImode constants)
274 case 'K': // Unsigned 16-bit constant
275 case 'L': // Signed 16-bit constant shifted left 16 bits
276 case 'M': // Constant larger than 31
277 case 'N': // Exact power of 2
278 case 'P': // Constant whose negation is a signed 16-bit constant
279 case 'G': // Floating point constant that can be loaded into a
281 case 'H': // Integer/Floating point constant that can be loaded
284 case 'm': // Memory operand. Note that on PowerPC targets, m can
286 // is therefore only safe to use `m' in an asm statement
288 // The asm statement must also use `%U<opno>' as a
294 // is not. Use es rather than m if you don't want the base
296 case 'e':
307 case 'Q': // Memory operand that is an offset from a register (it is
308 // usually better to use `m' or `es' in asm statements)
311 case 'Z': // Memory operand that is an indexed or indirect from a
312 // register (it is usually better to use `m' or `es' in
316 case 'a': // Address operand that is an indexed or indirect from a
320 case 'R': // AIX TOC entry
321 case 'S': // Constant suitable as a 64-bit mask operand
322 case 'T': // Constant suitable as a 32-bit mask operand
323 case 'U': // System V Release 4 small data area reference
324 case 't': // AND masks that can be performed by two rldic{l, r}
326 case 'W': // Vector constant that does not require memory
327 case 'j': // Vector constant that is all zeros.
337 case 'e':
338 case 'w':
339 // Two-character constraint; add "^" hint for later parsing.
355 return -1;
404 resetDataLayout("E-m:a-p:32:32-Fi32-i64:64-n32");
406 resetDataLayout("e-m:e-p:32:32-Fn32-i64:64-n32");
408 resetDataLayout("E-m:e-p:32:32-Fn32-i64:64-n32");
411 case llvm::Triple::Linux:
412 case llvm::Triple::FreeBSD:
413 case llvm::Triple::NetBSD:
418 case llvm::Triple::AIX:
463 DataLayout = "E-m:a-Fi64-i64:64-n32:64";
468 DataLayout = "e-m:e-Fn32-i64:64-n32:64";
471 DataLayout = "E-m:e";
474 DataLayout += "-Fn32";
477 DataLayout += "-Fi64";
479 DataLayout += "-i64:64-n32:64";
488 DataLayout += "-S128-v256:256:256-v512:512:512";
498 // For power8 and up, backend is able to inline 16-byte atomic lock free
501 if (!getTriple().isOSAIX() && hasFeature("quadword-atomics"))
509 // PPC64 Linux-specific ABI options.
520 case CC_Swift:
522 case CC_SwiftAsync: