Lines Matching full:features

32 /// configured set of features.
33 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
36   for (const auto &Feature : Features) {
517     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
519   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
534   Features["power9-vector"] = (CPU == "pwr9");
535   Features["crypto"] = llvm::StringSwitch<bool>(CPU)
540   Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
545   Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
551   Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
557   Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
562   Features["crbits"] = llvm::StringSwitch<bool>(CPU)
567   Features["vsx"] = llvm::StringSwitch<bool>(CPU)
573   Features["htm"] = llvm::StringSwitch<bool>(CPU)
580   Features["rop-protect"] = false;
582   Features["privileged"] = false;
586   Features["aix-small-local-exec-tls"] = false;
587   Features["aix-small-local-dynamic-tls"] = false;
590   Features["aix-shared-lib-tls-model-opt"] = false;
592   Features["spe"] = llvm::StringSwitch<bool>(CPU)
597   Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
605   Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
611   Features["isa-v30-instructions"] =
614   Features["quadword-atomics"] =
620   // Power10 includes all the same features as Power9 plus any features specific
623     initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
624     addP10SpecificFeatures(Features);
627   // Power11 includes all the same features as Power10 plus any features
630     initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
631     addP11SpecificFeatures(Features);
634   // Future CPU should include all of the features of Power 11 as well as any
635   // additional features (yet to be determined) specific to it.
637     initFeatureMap(Features, Diags, "pwr11", FeaturesVec);
638     addFutureSpecificFeatures(Features);
693   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
696 // Add any Power10 specific features.
698     llvm::StringMap<bool> &Features) const {
699   Features["htm"] = false; // HTM was removed for P10.
700   Features["paired-vector-memops"] = true;
701   Features["mma"] = true;
702   Features["power10-vector"] = true;
703   Features["pcrelative-memops"] = true;
704   Features["prefix-instrs"] = true;
705   Features["isa-v31-instructions"] = true;
708 // Add any Power11 specific features.
710     llvm::StringMap<bool> &Features) const {}
712 // Add features specific to the "Future" CPU.
714     llvm::StringMap<bool> &Features) const {}
750 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
754       Features["spe"] = true;
755     // If we're enabling any of the vsx based features then enable vsx and
768       Features["vsx"] = Features["altivec"] = true;
770       Features["power8-vector"] = true;
772       Features["power8-vector"] = Features["power9-vector"] = true;
774       Features["pcrelative-memops"] = true;
776       Features["prefix-instrs"] = true;
778       Features[Name] = true;
781       Features["efpu2"] = false;
783     // features.
785       Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
786           Features["float128"] = Features["power9-vector"] =
787               Features["paired-vector-memops"] = Features["mma"] =
788                   Features["power10-vector"] = false;
790       Features["power9-vector"] = Features["paired-vector-memops"] =
791           Features["mma"] = Features["power10-vector"] = false;
793       Features["paired-vector-memops"] = Features["mma"] =
794           Features["power10-vector"] = false;
796       Features["pcrelative-memops"] = false;
798       Features["prefix-instrs"] = false;
800       Features[Name] = false;