Lines Matching full:src
81 #define src r1 macro
109 vldr \vreg, [src, #\base]
111 vldr d0, [src, #\base + 8]
113 vldr d1, [src, #\base + 16]
115 vldr d2, [src, #\base + 24]
117 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
119 vldr d0, [src, #\base + 40]
121 vldr d1, [src, #\base + 48]
123 vldr d2, [src, #\base + 56]
128 vldr \vreg, [src, #\base]
130 vldr d0, [src, #\base + 8]
132 vldr d1, [src, #\base + 16]
134 vldr d2, [src, #\base + 24]
137 vldr d0, [src, #\base + 40]
139 vldr d1, [src, #\base + 48]
141 vldr d2, [src, #\base + 56]
166 vld1.8 {d0}, [src]! /* 14 words to go. */
168 vld1.8 {d0}, [src]! /* 12 words to go. */
170 vld1.8 {d0}, [src]! /* 10 words to go. */
172 vld1.8 {d0}, [src]! /* 8 words to go. */
174 vld1.8 {d0}, [src]! /* 6 words to go. */
176 vld1.8 {d0}, [src]! /* 4 words to go. */
178 vld1.8 {d0}, [src]! /* 2 words to go. */
182 ldrne tmp1, [src], #4
189 add src, src, tmp1
194 ldr tmp1, [src, #-60] /* 15 words to go. */
197 ldr tmp1, [src, #-56] /* 14 words to go. */
199 ldr tmp1, [src, #-52]
202 ldr tmp1, [src, #-48] /* 12 words to go. */
204 ldr tmp1, [src, #-44]
207 ldr tmp1, [src, #-40] /* 10 words to go. */
209 ldr tmp1, [src, #-36]
212 ldr tmp1, [src, #-32] /* 8 words to go. */
214 ldr tmp1, [src, #-28]
217 ldr tmp1, [src, #-24] /* 6 words to go. */
219 ldr tmp1, [src, #-20]
222 ldr tmp1, [src, #-16] /* 4 words to go. */
224 ldr tmp1, [src, #-12]
227 ldr tmp1, [src, #-8] /* 2 words to go. */
229 ldr tmp1, [src, #-4]
234 ldrhcs tmp1, [src], #2
235 ldrbne src, [src] /* Src is dead, use as a scratch. */
237 strbne src, [dst]
243 and tmp2, src, #7
255 /* SRC and DST have the same mutual 64-bit alignment, but we may
257 We bring SRC and DST into full 64-bit alignment. */
262 ldrmi tmp1, [src], #4
265 ldrhcs tmp1, [src], #2
266 ldrbne tmp2, [src], #1
280 vldr d0, [src, #0]
282 vldr d1, [src, #8]
284 vldr d0, [src, #16]
286 vldr d1, [src, #24]
288 vldr d0, [src, #32]
290 vldr d1, [src, #40]
292 vldr d0, [src, #48]
294 vldr d1, [src, #56]
296 add src, src, #64
306 add src, src, tmp1
310 vldr d0, [src, #-56] /* 14 words to go. */
312 vldr d0, [src, #-48] /* 12 words to go. */
314 vldr d0, [src, #-40] /* 10 words to go. */
316 vldr d0, [src, #-32] /* 8 words to go. */
318 vldr d0, [src, #-24] /* 6 words to go. */
320 vldr d0, [src, #-16] /* 4 words to go. */
322 vldr d0, [src, #-8] /* 2 words to go. */
325 sub src, src, #8
328 ldrd A_l, A_h, [src, #8]
330 ldrd A_l, A_h, [src, #16]
332 ldrd A_l, A_h, [src, #24]
334 ldrd A_l, A_h, [src, #32]
336 ldrd A_l, A_h, [src, #40]
338 ldrd A_l, A_h, [src, #48]
340 ldrd A_l, A_h, [src, #56]
342 ldrd A_l, A_h, [src, #64]!
351 add src, src, #8
356 we know that the src and dest are 64-bit aligned so we can use
363 add src, src, tmp1
366 ldrd A_l, A_h, [src, #-56] /* 14 words to go. */
368 ldrd A_l, A_h, [src, #-48] /* 12 words to go. */
370 ldrd A_l, A_h, [src, #-40] /* 10 words to go. */
372 ldrd A_l, A_h, [src, #-32] /* 8 words to go. */
374 ldrd A_l, A_h, [src, #-24] /* 6 words to go. */
376 ldrd A_l, A_h, [src, #-16] /* 4 words to go. */
378 ldrd A_l, A_h, [src, #-8] /* 2 words to go. */
383 ldrne tmp1, [src], #4
386 ldrhcs tmp1, [src], #2
387 ldrbne tmp2, [src]
404 vldr d3, [src, #0]
405 vldr d4, [src, #64]
406 vldr d5, [src, #128]
407 vldr d6, [src, #192]
408 vldr d7, [src, #256]
410 vldr d0, [src, #8]
411 vldr d1, [src, #16]
412 vldr d2, [src, #24]
413 add src, src, #32
422 add src, src, #3 * 64
426 add src, src, #2 * 64
434 add src, src, #3 * 64
438 vldr d7, [src, #64]
440 vldr d0, [src, #64 + 8]
442 vldr d1, [src, #64 + 16]
444 vldr d2, [src, #64 + 24]
446 add src, src, #96
457 /* Pre-bias src and dst. */
458 sub src, src, #8
460 pld [src, #8]
461 pld [src, #72]
463 pld [src, #136]
464 ldrd A_l, A_h, [src, #8]
466 ldrd B_l, B_h, [src, #16]
468 ldrd C_l, C_h, [src, #24]
470 pld [src, #200]
471 ldrd D_l, D_h, [src, #32]!
475 pld [src, #232]
477 ldrd A_l, A_h, [src, #40]
479 ldrd B_l, B_h, [src, #48]
481 ldrd C_l, C_h, [src, #56]
483 ldrd D_l, D_h, [src, #64]!
487 ldrd A_l, A_h, [src, #8]
489 ldrd B_l, B_h, [src, #16]
491 ldrd C_l, C_h, [src, #24]
493 ldrd D_l, D_h, [src, #32]
497 add src, src, #40
512 pld [src]
513 pld [src, #64]
518 pld [src, #(2 * 64)]
522 ldrmi tmp1, [src], #4
525 ldrbne tmp1, [src], #1
526 ldrhcs tmp2, [src], #2
530 pld [src, #(3 * 64)]
534 pld [src, #(4 * 64)]
537 vld1.8 {d0-d3}, [src]!
538 vld1.8 {d4-d7}, [src]!
542 pld [src, #(4 * 64)]
544 vld1.8 {d0-d3}, [src]!
546 vld1.8 {d4-d7}, [src]!
555 sub src, src, #4
558 ldr A_l, [src, #4]
559 ldr A_h, [src, #8]
561 ldr B_l, [src, #12]
562 ldr B_h, [src, #16]
564 ldr C_l, [src, #20]
565 ldr C_h, [src, #24]
567 ldr D_l, [src, #28]
568 ldr D_h, [src, #32]!
572 pld [src, #(5 * 64) - (32 - 4)]
574 ldr A_l, [src, #36]
575 ldr A_h, [src, #40]
577 ldr B_l, [src, #44]
578 ldr B_h, [src, #48]
580 ldr C_l, [src, #52]
581 ldr C_h, [src, #56]
583 ldr D_l, [src, #60]
584 ldr D_h, [src, #64]!
588 ldr A_l, [src, #4]
589 ldr A_h, [src, #8]
591 ldr B_l, [src, #12]
592 ldr B_h, [src, #16]
594 ldr C_l, [src, #20]
595 ldr C_h, [src, #24]
597 ldr D_l, [src, #28]
598 ldr D_h, [src, #32]
603 add src, src, #36