70 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,
72 void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,  in evergreen_hdmi_update_acr()  argument
85 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,  in evergreen_hdmi_update_acr()
88 		WREG32(HDMI_ACR_PACKET_CONTROL + offset,  in evergreen_hdmi_update_acr()
92 	WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));  in evergreen_hdmi_update_acr()
93 	WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);  in evergreen_hdmi_update_acr()
95 	WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));  in evergreen_hdmi_update_acr()
96 	WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);  in evergreen_hdmi_update_acr()
98 	WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));  in evergreen_hdmi_update_acr()
99 	WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);  in evergreen_hdmi_update_acr()
221 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,
223 void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,  in evergreen_set_avi_packet()  argument
228 	WREG32(AFMT_AVI_INFO0 + offset,  in evergreen_set_avi_packet()
230 	WREG32(AFMT_AVI_INFO1 + offset,  in evergreen_set_avi_packet()
232 	WREG32(AFMT_AVI_INFO2 + offset,  in evergreen_set_avi_packet()
234 	WREG32(AFMT_AVI_INFO3 + offset,  in evergreen_set_avi_packet()
237 	WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,  in evergreen_set_avi_packet()
325 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset);
326 void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)  in dce4_set_vbi_packet()  argument
331 	WREG32(HDMI_VBI_PACKET_CONTROL + offset,  in dce4_set_vbi_packet()
337 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc);
338 void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)  in dce4_hdmi_set_color_depth()  argument
345 	val = RREG32(HDMI_CONTROL + offset);  in dce4_hdmi_set_color_depth()
372 	WREG32(HDMI_CONTROL + offset, val);  in dce4_hdmi_set_color_depth()
375 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset);
376 void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)  in dce4_set_audio_packet()  argument
381 	WREG32(AFMT_INFOFRAME_CONTROL0 + offset,  in dce4_set_audio_packet()
384 	WREG32(AFMT_60958_0 + offset,  in dce4_set_audio_packet()
387 	WREG32(AFMT_60958_1 + offset,  in dce4_set_audio_packet()
390 	WREG32(AFMT_60958_2 + offset,  in dce4_set_audio_packet()
398 	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,  in dce4_set_audio_packet()
401 	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,  in dce4_set_audio_packet()
406 	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,  in dce4_set_audio_packet()
411 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute);
412 void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)  in dce4_set_mute()  argument
418 		WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);  in dce4_set_mute()
420 		WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);  in dce4_set_mute()
438 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,  in evergreen_hdmi_enable()
443 			WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_hdmi_enable()
446 			WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,  in evergreen_hdmi_enable()
449 			WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_hdmi_enable()
453 		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_hdmi_enable()
455 		WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);  in evergreen_hdmi_enable()
461 		  enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);  in evergreen_hdmi_enable()
483 		WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_dp_enable()
486 		WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,  in evergreen_dp_enable()
491 			val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);  in evergreen_dp_enable()
499 			WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);  in evergreen_dp_enable()
502 		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,  in evergreen_dp_enable()
508 		WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);  in evergreen_dp_enable()
509 		WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,  in evergreen_dp_enable()